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| FDC37C669 PC 98/99 Compliant Super I/O Floppy Disk Controller with Infrared Support FEATURES * * * * 5 Volt Operation Intelligent Auto Power Management 16 Bit Address Qualification (Optional) 2.88MB Super I/O Floppy Disk Controller - Licensed CMOS 765B Floppy Disk Controller - Software and Register Compatible with SMSC's Proprietary 82077AA Compatible Core - Supports Two Floppy Drives Directly - Supports Vertical Recording Format - 16 Byte Data FIFO - 100% IBM Compatibility - Detects All Overrun and Underrun Conditions - Sophisticated Power Control Circuitry (PCC) Including Multiple Powerdown Modes for Reduced Power Consumption - DMA Enable Logic - Data Rate and Drive Control Registers - Swap Drives A and B - Non-Burst Mode DMA option - 48 Base I/O Address, Seven IRQ and Three DMA Options Floppy Disk Available on Parallel Port Pins Enhanced Digital Data Separator - 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250 Kbps Data Rates - Programmable Precompensation Modes Serial Ports - Two High Speed NS16C550 Compatible UARTs with Send/Receive 16 Byte FIFOs - Supports 230k and 460k Baud - Programmable Baud Rate Generator Modem Control Circuitry Infrared - IrDA (HPSIR) and Amplitude Shift Keyed IR (ASKIR) - Alternate IR Pins (Optional) - 96 Base I/O Address and Eight IRQ Options Multi-Mode Parallel Port with ChiProtect - Standard Mode - IBM PC/XT, PC/AT, and PS/2 Compatible Bidirectional Parallel Port - Enhanced Parallel Port (EPP) Compatible - EPP 1.7 and EPP 1.9 (IEEE 1284 Compliant) - Enhanced Capabilities Port (ECP) Compatible (IEEE 1284 Compliant) - Incorporates ChiProtect Circuitry for Protection Against Damage Due to Printer Power-On - 192 Base I/O Address, Seven IRQ and Three DMA Options ISA Host Interface IDE Interface (Optional) - On-Chip Decode and Select Logic Compatible with IBM PC/XT and PC/AT Embedded Hard Disk Drives - 48 Base I/O Address and Seven IRQ Options Game Port Select Logic - 48 Base I/O Addresses General Purpose Address Decoder - 16 Byte Block decode - 48 Base I/O Address Options 100 Pin QFP and TQFP Package - * * * * * * * * * TABLE OF CONTENTS FEATURES ............................................................................................................................................ 1 GENERAL DESCRIPTION..................................................................................................................... 3 PIN CONFIGURATION ........................................................................................................................... 4 DESCRIPTION OF PIN FUNCTIONS ..................................................................................................... 6 FUNCTIONAL DESCRIPTION ............................................................................................................. 17 SUPER I/O REGISTERS.................................................................................................................. 17 HOST PROCESSOR INTERFACE.................................................................................................. 17 FLOPPY DISK CONTROLLER........................................................................................................ 18 FLOPPY DISK CONTROLLER INTERNAL REGISTERS ................................................................ 18 COMMAND SET/DESCRIPTIONS....................................................................................................... 41 INSTRUCTION SET.............................................................................................................................. 45 PARALLEL PORT FLOPPY DISK CONTROLLER ................................................................................ 71 SERIAL PORT (UART) ......................................................................................................................... 73 INFRARED INTERFACE........................................................................................................................ 87 PARALLEL PORT ................................................................................................................................ 88 IBM XT/AT COMPATIBLE, BI-DIRECTIONAL AND EPP MODES ................................................... 90 EXTENDED CAPABILITIES PARALLEL PORT .............................................................................. 96 AUTO POWER MANAGEMENT .......................................................................................................... 109 INTEGRATED DRIVE ELECTRONICS INTERFACE......................................................................... 114 CONFIGURATION .............................................................................................................................. 118 OPERATIONAL DESCRIPTION ......................................................................................................... 137 MAXIMUM GUARANTEED RATINGS........................................................................................... 137 DC ELECTRICAL CHARACTERISTICS....................................................................................... 137 TIMING DIAGRAMS............................................................................................................................ 140 ECP PARALLEL PORT TIMING..................................................................................................... 157 2 GENERAL DESCRIPTION The SMSC FDC37C669 PC 95 Compatible Super I/O Floppy Disk Controller with Infrared Support utilizes SMSC's proven SuperCell technology for increased product reliability and functionality. The FDC37C669 is PC95 compliant and is optimized for motherboard applications. The FDC37C669 supports both 1 Mbps and 2 Mbps data rates and vertical vertical recording operation at 1 Mbps Data Rate. The FDC37C669 incorporates SMSC's true CMOS 765B floppy disk controller, advanced digital data separator, 16 byte data FIFO, two 16C550 compatible UARTs, one Multi-Mode parallel port which includes ChiProtect circuitry plus EPP and ECP support, IDE interface, on-chip 12 mA AT bus drivers, game port chip select and two floppy direct drive support. The true CMOS 765B core provides 100% compatibility with IBM PC/XT and PC/AT architectures in addition to providing data overflow and underflow protection. The SMSC advanced digital data separator incorporates SMSC's patented data separator technology, allowing for ease of testing and use. Both on-chip UARTs are compatible with the NS16C550. One UART includes additional support for a Serial Infrared Interface, complying with IrDA, HPSIR, and ASKIR formats (used by Sharp, Apple Newton, and other PDAs). The parallel port, the IDE interface, and the game port select logic are compatible with IBM PC/AT architectures. The FDC37C669 incorporates sophisticated power control circuitry (PCC). The PCC supports multiple low power down modes. The FDC37C669 Floppy Disk Controller incorporates Software Configurable Logic (SCL) for ease of use. Use of the SCL feature allows programmable system configuration of key functions such as the FDC, parallel port, and UARTs. The parallel port ChiProtect prevents damage caused by the printer being powered when the FDC37C669 is not powered. The FDC37C669 does not require any external filter components, and is, therefore easy to use and offers lower system cost and reduced board area. The FDC37C669 is software and register compatible with SMSC's proprietary 82077AA core. 3 nRTS1 nCTS1 nDTR1 nRI1 nDCD1 nRI2 nDCD2 RXD2/IRRX TXD2/IRTX nDSR2 nRTS2 nCTS2 nDTR2 DRV2/ADRX/IRQ_B VSS nDACK_C A10 NC DRQ_C IOCHRDY 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 PIN CONFIGURATION FDC37C669 100 PIN QFP 4 DRVDEN0 nMTR0 nDS1 nDS0 nMTR1 VSS nDIR nSTEP nWDATA nWGATE nHDSEL nINDEX nTRK0 nWRTPRT VCC nRDATA nDSKCHG DRVDEN1 IRQ_A CLK14 DRQ_A nDACK_A IRQIN nIDEEN/IRQ_H nHDCS0/IRRX2 nHDCS1/IRTX2 nCS A0 A1 A2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 D2 D1 D0 VSS AEN nIOW nIOR A9 A8 A7 IRQ_F IRQ_E IRQ_D IRQ_C nDACK_B TC A6 A5 A4 A3 nDSR1 TXD1 RXD1 nSTROBE nAUTOFD nERROR nINIT nSLCTIN VCC PD0 PD1 PD2 PD3 VSS PD4 PD5 PD6 PD7 nACK BUSY PE SLCT PWRGD/GAMECS RESET D7 D6 D5 D4 DRQ_B D3 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 IOCHRDY DRQ_C NC A10 nDACK_C VSS DRV2/ADRX/IRQ_B nDTR2 nCTS2 nRTS2 nDSR2 TXD2/IRTX RXD2/IRRX nDCD2 nRI2 nDCD1 nRI1 nDTR1 nCTS1 nRTS1 nDSR1 TXD1 RXD1 nSTROBE nAUTOFD DRVDEN0 nMTR0 nDS1 nDS0 nMTR1 VSS nDIR nSTEP nWDATA nWGATE nHDSEL nINDEX nTRK0 nWRTPRT VCC nRDATA nDSKCHG DRVDEN1 IRQ_A CLK14 DRQ_A nDACK_A IRQIN nIDEEN/IRQ_H nHDCS0/IRRX2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 FDC37C669 100 PIN TQFP nERROR nINIT nSLCTIN VCC PD0 PD1 PD2 PD3 VSS PD4 PD5 PD6 PD7 nACK BUSY PE SLCT PWRGD/GAMECS RESET D7 D6 D5 D4 DRQ_B D3 nHDCS1/IRTX2 nCS A0 A1 A2 A3 A4 A5 A6 TC nDACK_B IRQ_C IRQ_D IRQ_E IRQ_F A7 A8 A9 nIOR nIOW AEN VSS D0 D1 D2 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 5 DESCRIPTION OF PIN FUNCTIONS QFP/ TQFP PIN NO. NAME Data Bus 0-7 SYMBOL D0-D7 BUFFER TYPE DESCRIPTION The data bus connection used by the host microprocessor to transmit data to and from the chip. These pins are in a highimpedance state when not in the output mode. This active low signal is issued by the host microprocessor to indicate a read operation. This active low signal is issued by the host microprocessor to indicate a write operation. Active high Address Enable indicates DMA operations on the host data bus. Used internally to qualify appropriate address decodes. These host address bits determine the I/O address to be accessed during nIOR and nIOW cycles. These bits are latched internally by the leading edge of nIOR and nIOW. All internal address decodes use the full A0 to A10 address bits. This active high output is the DMA request for byte transfers of data between the host and the chip. This signal is cleared on the last byte of the data transfer by the nDACK signal going low (or by nIOR going low if nDACK was already low as in demand mode). An active low input acknowledging the request for a DMA transfer of data between the host and the chip. This input enables the DMA read or write internally. This signal indicates to the chip that DMA data transfer is complete. TC is only accepted when nDACK_x is low. In AT and PS/2 model 30 modes, TC is active high and in PS/2 mode, TC is active low. HOST PROCESSOR INTERFACE 48-51 53-56 I/O24 44 45 46 nI/O Read nI/O Write Address Enable nIOR nIOW AEN I I I 28-34 41-43, 97 I/O Address A0-A10 I 21,52, 99 DMA Request A, B, C DRQ_A DRQ_B DRQ_C O24 22,36, 96 nDMA Acknowledge A, B, C nDACK_A nDACK_B nDACK_C TC I 35 Terminal Count I 6 DESCRIPTION OF PIN FUNCTIONS QFP/ TQFP PIN NO. 19, 37-40, NAME Interrupt Request A, C, D, E, F, SYMBOL IRQ_A IRQ_C IRQ_D IRQ_E IRQ_F OD24 27 Chip Select Input nCS I If EPP or ECP Mode is enabled, this output is pulsed low, then released to allow sharing of interrupts. When enabled, this active low pin serves as an input for an external decoder circuit which is used to qualify address lines above A10. This active high signal resets the chip and must be valid for 500 ns minimum. The effect on the internal registers is described in the appropriate section. The configuration registers are not affected by this reset. Raw serial bit stream from the disk drive, low active. Each falling edge represents a flux transition of the encoded data. This active low high current driver allows current to flow through the write head. It becomes active just prior to writing to the diskette. This active low high current driver provides the encoded data to the disk drive. Each falling edge causes a flux transition on the media. This high current output selects the floppy disk side for reading or writing. A logic "1" on this pin means side 0 will be accessed, while a logic "0" means side 1 will be accessed. BUFFER TYPE O24 DESCRIPTION The interrupt request from the logical device or IRQIN is output on one of the IRQA-G signals. Refer to the configuration registers for more information. 57 Reset RESET IS FLOPPY DISK INTERFACE 16 nRead Disk Data nRDATA IS 10 nWrite Gate nWGATE OD48 9 nWrite Data nWDATA OD48 11 nHead Select nHDSEL OD48 7 DESCRIPTION OF PIN FUNCTIONS QFP/ TQFP PIN NO. 7 NAME Direction Control SYMBOL nDIR BUFFER TYPE OD48 DESCRIPTION This high current low active output determines the direction of the head movement. A logic "1" on this pin means outward motion, while a logic "0" means inward motion. This active low high current driver issues a low pulse for each track-to-track movement of the head. This input senses that the drive door is open or that the diskette has possibly been changed since the last drive selection. This input is inverted and read via bit 7 of I/O address 3F7H. Active low open drain outputs select drives 0-1. These active low open drain outputs select motor drives 0-1. Indicates the drive and media selected. Refer to configuration registers CR03, CR0B, CR1F. This active low Schmitt Trigger input senses from the disk drive that a disk is write protected. Any write command is ignored. This active low Schmitt Trigger input senses from the disk drive that the head is positioned over the outermost track. This active low Schmitt Trigger input senses from the disk drive that the head is positioned over the beginning of a track, as marked by an index hole. Indicates the drive and media selected. Refer to configuration registers CR03, CR0B, CR1F. Receiver serial data input for port 2. IR Receive Data 8 nStep Pulse nSTEP OD48 17 Disk Change nDSKCHG IS 4,3 2,5 1 nDrive Select O,1 nMotor On 0,1 DRVDEN0 nDS0,1 nMTR0,1 DRVDEN0 OD48 OD48 OD48 14 nWrite Protected nWRTPRT IS 13 wTrack 00 nTRK00 IS 12 nIndex nINDEX IS 18 DRVDEN1 DRVDEN 1 OD48 SERIAL PORT INTERFACE 88 Receive Data 2 RXD2/IRRX I 8 DESCRIPTION OF PIN FUNCTIONS QFP/ TQFP PIN NO. 89 78 79 81,91 NAME Transmit Data 2 Receive Data 1 Transmit Data 1 nRequest to Send SYMBOL TXD2/IRTX RXD1 TXD1 nRTS1 nRTS2 (SYSOPT) (System Option) BUFFER TYPE O24 I 024 O4 DESCRIPTION Transmit serial data output for port 2. IR transmit data. Reciever serial data input for port 1. Transmit serial data output for port 1. Active low Request to Send outputs for the Serial Port. Handshake output signal notifies modem that the UART is ready to transmit data. This signal can be programmed by writing to bit 1 of Modem Control Register (MCR). The hardware reset will reset the nRTS signal to inactive mode (high). Forced inactive during loop mode operation. At the trailing edge of hardware reset, the nRTS2 input is latched to determine the configuration base address. 0 : INDEX Base I/O Address = 3F0 Hex 1 : INDEX Base I/O Address = 370 Hex 83,93 nData Terminal Ready nDTR1 nDTR2 O4 Active low Data Terminal Ready outputs for the serial port. Handshake output signal notifies modem that the UART is ready to establish data communication link. This signal can be programmed by writing to bit 0 of Modem Control Register (MCR). The hardware reset will reset the nDTR signal to inactive mode (high). Forced inactive during loop mode operation. 9 DESCRIPTION OF PIN FUNCTIONS QFP/ TQFP PIN NO. 82,92 NAME nClear to Send SYMBOL nCTS1 nCTS2 BUFFER TYPE I DESCRIPTION Active low Clear to Send inputs for the serial port. Handshake signal which notifies the UART that the modem is ready to receive data. The CPU can monitor the status of nCTS signal by reading bit 4 of Modem Status Register (MSR). A nCTS signal state change from low to high after the last MSR read will set MSR bit 0 to a 1. If bit 3 of Interrupt Enable Register is set, the interrupt is generated when nCTS changes state. The nCTS signal has no effect on the transmitter. Note: Bit 4 of MSR is the complement of nCTS. Active low Data Set Ready inputs for the serial port. Handshake signal which notifies the UART that the modem is ready to establish the communication link. The CPU can monitor the status of nDSR signal by reading bit 5 of Modem Status Register (MSR). A nDSR signal state change from low to high after the last MSR read will set MSR bit 1 to a 1. If bit 3 of Interrupt Enable Register is set, the interrupt is generated when nDSR changes state. Note: Bit 5 of MSR is the complement of nDSR. Active low Data Carrier Detect inputs for the serial port. Handshake signal which notifies the UART that carrier signal is detected by the modem. The CPU can monitor the status of nDCD signal by reading bit 7 of Modem Status Register (MSR). A nDCD signal state change from low to high after the last MSR read will set MSR bit 3 to a 1. If bit 3 of Interrupt Enable Register is set, the interrupt is generated when nDCD changes state. Note: Bit 7 of MSR is the complement of nDCD. 80,90 nData Set Ready nDSR1 nDSR2 I 85,87 nData Carrier Detect nDCD1 nDCD2 I 10 DESCRIPTION OF PIN FUNCTIONS QFP/ TQFP PIN NO. 84,86 NAME nRing Indicator SYMBOL nRI1 nRI2 BUFFER TYPE I DESCRIPTION Active low Ring Indicator inputs for the serial port. Handshake signal which notifies the UART that the telephone ring signal is detected by the modem. The CPU can monitor the status of nRI signal by reading bit 6 of Modem Status Register (MSR). A nRI signal state change from low to high after the last MSR read will set MSR bit 2 to a 1. If bit 3 of Interrupt Enable Register is set, the interrupt is generated when nRI changes state. Note: Bit 6 of MSR is the complement of nRI. This active low output selects the printer. This is the complement of bit 3 of the Printer Control Register. Refer to Parallel Port description for use of this pin in ECP and EPP mode. This output is bit 2 of the printer control register. This is used to initiate the printer when low. Refer to Parallel Port description for use of this pin in ECP and EPP mode. This output goes low to cause the printer to automatically feed one line after each line is printed. The nAUTOFD output is the complement of bit 1 of the Printer Control Register. Refer to Parallel Port description for use of this pin in ECP and EPP mode. PARALLEL PORT INTERFACE 73 nPrinter Select Input nSLCTIN OD24 0P24 74 nInitiate Output nINIT OD24 0P24 76 nAutofeed Output nAUTOFD OD24 0P24 11 DESCRIPTION OF PIN FUNCTIONS QFP/ TQFP PIN NO. 77 NAME nStrobe Output SYMBOL nSTROBE BUFFER TYPE OD24 DESCRIPTION An active low pulse on this output is used to strobe the printer data into the printer. The nSTROBE output is the complement of bit 0 of the Printer Control Register. Refer to Parallel Port description for use of this pin in ECP and EPP mode. This is a status output from the printer, a high indicating that the printer is not ready to receive new data. Bit 7 of the Printer Status Register is the complement of the BUSY input. Refer to Parallel Port description for use of this pin in ECP and EPP mode. A low active output from the printer indicating that it has received the data and is ready to accept new data. Bit 6 of the Printer Status Register reads the nACK input. Refer to Parallel Port description for use of this pin in ECP and EPP mode. Another status output from the printer, a high indicating that the printer is out of paper. Bit 5 of the Printer Status Register reads the PE input. Refer to Parallel Port description for use of this pin in ECP and EPP mode. This high active output from the printer indicates that it has power on. Bit 4 of the Printer Status Register reads the SLCT input. Refer to Parallel Port description for use of this pin in ECP and EPP mode. A low on this input from the printer indicates that there is a error condition at the printer. Bit 3 of the Printer Status register reads the nERR input. Refer to Parallel Port description for use of this pin in ECP and EPP mode. 0P24 61 Busy BUSY I 62 nAcknowledge nACK I 60 Paper End PE I 59 Printer Selected Status SLCT I 75 nError nERROR I 12 DESCRIPTION OF PIN FUNCTIONS QFP/ TQFP PIN NO. 63-66 68-71 100 IOCHRDY IOCHRDY OD24P NAME Port Data SYMBOL PD0-PD7 BUFFER TYPE I/O24 DESCRIPTION The bi-directional parallel data bus is used to transfer information between CPU and peripherals. In EPP mode, this pin is pulled low to extend the read/write command. This pin has an internal pull-up. This active low signal is active when the IDE is enabled and the I/O address is accessing an IDE register. The interrupt request from a logical device or IRQIN may be output on the IRQH signal. Refer to the configuration registers for more information. If EPP or ECP Mode is enabled, this output is pulsed low, then released to allow sharing of interrupts. This is the Hard Disk Chip select corresponding to the eight control block addresses. Alternate IR Receive input This is the corresponding register. Hard Disk Chip to the alternate select status IDE/ALT IR PINS 24 nIDE Enable nIDEEN O24P (Note 1) Interrupt Request H IRQ_H 024 OD24 25 nIDE Chip Select 0 nHDCS0 O24P (Note 1) IRRX2 26 nIDE Chip Select 1 IRRX2 nHDCS1 I O24P (Note 1) IR Transmit 2 20 CLOCK 14 IRTX2 CLK14 O24P ICLK Alternate IR transmit output The external connection to a single source 14.318 MHz clock. MISCELLANEOUS 13 DESCRIPTION OF PIN FUNCTIONS QFP/ TQFP PIN NO. 94 NAME Drive 2 SYMBOL DRV2 BUFFER TYPE I DESCRIPTION In PS/2 mode, this input indicates whether a second drive is connected; DRV2 should be low if a second drive is connected. This status is reflected in a read of Status Register A. Active low address decode out: used to decode a 1, 8, or 16 byte address block. (An external pull-up is required). Refer to Configuration registers CR03, CR08 and CR09 for more information. This pin has a 30ua internal pull-up. The interrupt request from a logical device or IRQIN may be output on IRQ_B. Refer to the configuration registers for more information. (If EPP or ECP Mode is enabled, this output is pulsed low, then released to allow sharing of interrupts.) This pin is used to steer an interrupt signal from an external device onto one of eight IRQ outputs IRQA-H. This active high input indicates that the power (VCC) is valid. For device operation, PWRGD must be active. When PWRGD is inactive, all inputs to Mercury are disconnected and put into a low power mode; all outputs are put into high impedance. The contents of all registers are preserved as long as VCC has a valid value. The driver current drain in this mode drops to ISTBY - standby current. This input has an internal 30ua pull-up. This is the Game Port Chip Select output active low. It will go active when the I/O address, qualified by AEN, matches that selected in Configuration register CR1E. No Connect Address X nADRX OD24 Interrupt Request B IRQ_B 024 (OD24) 23 IRQIN I 58 PWRGD I nGAMECS O4 98 I/O Power NC 14 DESCRIPTION OF PIN FUNCTIONS QFP/ TQFP PIN NO. 15,72 6,47, 67,95 NAME Power Ground SYMBOL VCC GND BUFFER TYPE DESCRIPTION Positive Supply Voltage. Ground Supply. Note 1: Refer to Configuration Register 00 for information on the pull-ups for these pins! Note IDE does not decode for 377, 3F7 Note RI and the Serial interrupt is always active if system power is applied to the chip. BUFFER TYPE DESCRIPTIONS BUFFER TYPE I/O24 O24 OD48 O4 OD24 OD24P OP24 024P OCLK ICLK I IS DESCRIPTION Input/Output. 24 mA sink; 12 mA source Output. 24 mA sink; 12 mA source Open drain. 48 mA sink Output. 4 mA sink; 2 mA source Output. 24 mA sink Open drain. 24 mA sink; 30A source Output. 24 mA sink; 4 mA source Output. 24 mA sink; 12 mA source; with 30A pull-up Output to external crystal Input to Crystal Oscillator Circuit (CMOS levels) Input TTL compatible. Input with Schmitt Trigger. 15 5V Vcc (2) Vss (4) PWRGD POWER MANAGEMENT MULTI-MODE PARALLEL PORT/FDC MUX PD0-7 BUSY, SLCT, PE, nERROR, nACK nSTROBE, nSLCTIN, DATA BUS nCS ADDRESS BUS nIOR nIOW AEN A0-A10 CONTROL BUS HOST DRQ_A-C nDACK_A-C CPU INTERFACE WDATA WCLOCK 16C550 COMPATIBLE SERIAL PORT 2 WITH INFRARED CONFIGURATION REGISTERS GENERAL PURPOSE ADDRESS DECODER nINIT, nAUTOFD ADRX TXD1, nCTS1, nRTS1 16C550 COMPATIBLE SERIAL PORT 1 RXD1 nDSR1, nDCD1, nRI, nDTR1 D0-D7 TXD2(IRTX),nCTS2,nRTS2 RXD2(IRRX) nDSR2,nDCD2,nRI2,nDTR2 TC IRQA IRQ_C-F RESET SMSC PROPRIETARY 82077 COMPATIBLE VERTICAL FLOPPYDISK CONTROLLER CORE DIGITAL DATA SEPARATOR WITH WRITE PRECOMPENSATION RCLOCK RDATA nIDEEN(IRQH) IDE INTERFACE nHDCSO(IRRX2) nHDCS1(IRTX2) IRQIN CLOCK IOCHRDY GEN nINDEX nTRK0 14.318 CLOCK nDIR nSTEP nDS0,1,2 nMTR0,1,2 nWDATA nRDATA GAME PORT DECODER nDSKCHG DRVDEN0 nWRPRT DRVDEN1 nWGATE DRV2(nADRX)(IRQB) nGAMECS FIGURE 1 - FDC37C669 BLOCK DIAGRAM 16 FUNCTIONAL DESCRIPTION SUPER I/O REGISTERS The address map, shown below in Table 1, shows the addresses of the different blocks of the Super I/O immediately after power up. The base addresses of the FDC, IDE, serial and parallel ports can be moved via the configuration registers. Some addresses are used to access more than one register. HOST PROCESSOR INTERFACE The host processor communicates with the FDC37C669 through a series of read/write registers. The port addresses for these registers are shown in Table 1. Register access is accomplished through programmed I/O or DMA transfers. All registers are 8 bits wide except the IDE data register at port 1F0H which is 16 bits wide. All host interface output buffers are capable of sinking a minimum of 12 mA. ADDRESS Base +0,1 Base +[2:5, 7] Base +[0:7] Base +[0:7] Table 1 - FDC37C669 Block Addresses BLOCK NAME NOTES Configuration Floppy Disk Floppy Disk Serial Port Com 1 Serial Port Com 2 Parallel Port Write only; Note 1, 2 Read only; Disabled at power up; Note 2 Disabled at power up; Note 2 Disabled at power up; Note 2 Disabled at power up; Note 2 Disabled at power up; Note 2 3F0, 3F1 or 370, 371 Base +[0:3] all modes Base +[4:7] for EPP Base +[400:403] for ECP Base1 +[0:7] Base2 +[6] Note 1: IDE Disabled at power up; Note 2 Note 2: Configuration registers can only be modified in configuration mode, refer to the configuration register description for more information. Access to status registers A and B of the floppy disk is disabled in configuration mode. The base addresses must be set in the configuration registers before accessing the logical devices. 17 FLOPPY DISK CONTROLLER The Floppy Disk Controller (FDC) provides the interface between a host microprocessor and the floppy disk drives. The FDC integrates the functions of the Formatter/Controller, Digital Data Separator, Write Precompensation and Data Rate Selection logic for an IBM XT/AT compatible FDC. The true CMOS 765B core guarantees 100% IBM PC XT/AT compatibility in addition to providing data overflow and underflow protection. The FDC37C669 is compatible to the 82077AA using SMSC's proprietary floppy disk controller core. FLOPPY DISK REGISTERS CONTROLLER INTERNAL The Floppy Disk Controller contains eight internal registers which facilitate the interfacing between the host microprocessor and the disk drive. Table 2 shows the addresses required to access these registers. Registers other than the ones shown are not supported. The rest of the FDC description assumes the Base I/O Address is 3F0. Table 2 - Status, Data and Control Registers BASE I/O ADDRESS +0 +1 +2 +3 +4 +4 +5 +6 +7 +7 R R R/W R/W R W R/W R W REGISTER Status Register A Status Register B Digital Output Register Tape Drive Register Main Status Register Data Rate Select Register Data (FIFO) Reserved Digital Input Register Configuration Control Register SRA SRB DOR TSR MSR DSR FIFO DIR CCR For information on the floppy disk on Parallel Port pins, refer to Configuration Register CR4 and Parallel Port Floppy Disk Controller description. 18 STATUS REGISTER A (SRA) Address 3F0 READ ONLY This register is read-only and monitors the state of the FINTR pin and several disk interface pins, PS/2 Mode 7 INT PENDING RESET COND. 0 6 nDRV2 N/A 5 STEP 0 in PS/2 and Model 30 modes. The SRA can be accessed at any time when in PS/2 mode. In the PC/AT mode the data bus pins D0 - D7 are held in a high impedance state for a read of address 3F0. 4 3 2 1 nWP N/A 0 DIR 0 nTRK0 HDSEL nINDX N/A 0 N/A BIT 0 DIRECTION Active high status indicating the direction of head movement. A logic "1" indicating inward direction a logic "0" outward. BIT 1 nWRITE PROTECT Active low status of the WRITE PROTECT disk interface input. A logic "0" indicating that the disk is write protected. BIT 2 nINDEX Active low status of the INDEX disk interface input. BIT 3 HEAD SELECT Active high status of the HDSEL disk interface input. A logic "1" selects side 1 and a logic "0" selects side 0. BIT 4 nTRACK 0 Active low status of the TRK0 disk interface input. BIT 5 STEP Active high status of the STEP output disk interface output pin. BIT 6 nDRV2 Active low status of the DRV2 disk interface input pin, indicating that a second drive has been installed. BIT 7 INTERRUPT PENDING Active high bit indicating the state of the Floppy Disk Interrupt output. 19 PS/2 Model 30 Mode 7 INT PENDING RESET COND. 0 6 DRQ 0 5 STEP F/F 0 4 3 2 INDX N/A 1 WP N/A 0 nDIR 1 TRK0 nHDSEL N/A 1 BIT 0 nDIRECTION Active low status indicating the direction of head movement. A logic "0" indicating inward direction a logic "1" outward. BIT 1 WRITE PROTECT Active high status of the WRITE PROTECT disk interface input. A logic "1" indicating that the disk is write protected. BIT 2 INDEX Active high status of the INDEX disk interface input. BIT 3 nHEAD SELECT Active low status of the HDSEL disk interface input. A logic "0" selects side 1 and a logic "1" selects side 0. BIT 4 TRACK 0 Active high status of the TRK0 disk interface input. BIT 5 STEP Active high status of the latched STEP disk interface output pin. This bit is latched with the STEP output going active, and is cleared with a read from the DIR register, or with a hardware or software reset. BIT 6 DMA REQUEST Active high status of the DRQ output pin. BIT 7 INTERRUPT PENDING Active high bit indicating the state of the Floppy Disk Interrupt output. 20 STATUS REGISTER B (SRB) Address F1 READ ONLY This register is read-only and monitors the state of several disk interface pins, in PS/2 and Model PS/2 Mode 7 1 RESET COND. 1 6 1 1 5 4 30 modes. The SRB can be accessed at any time when in PS/2 mode. In the PC/AT mode the data bus pins D0 - D7 are held in a high impedance state for a read of address 3F1. 3 2 1 MOT EN1 0 0 MOT EN0 0 DRIVE WDATA RDATA WGATE SEL0 TOGGLE TOGGLE 0 0 0 0 BIT 0 MOTOR ENABLE 0 Active high status of the MTR0 disk interface output pin. This bit is low after a hardware reset and unaffected by a software reset. BIT 1 MOTOR ENABLE 1 Active high status of the MTR1 disk interface output pin. This bit is low after a hardware reset and unaffected by a software reset. BIT 2 WRITE GATE Active high status of the WGATE disk interface output. BIT 3 READ DATA TOGGLE Every inactive edge of the RDATA input causes this bit to change state. BIT 4 WRITE DATA TOGGLE Every inactive edge of the WDATA input causes this bit to change state. BIT 5 DRIVE SELECT 0 Reflects the status of the Drive Select 0 bit of the DOR (address 3F2 bit 0). This bit is cleared after a hardware reset, it is unaffected by a software reset. BIT 6 RESERVED Always read as a logic "1". BIT 7 RESERVED Always read as a logic "1". 21 PS/2 Model 30 Mode 7 nDRV2 RESET COND. N/A 6 nDS1 1 5 nDS0 1 4 WDATA F/F 0 3 RDATA F/F 0 2 WGATE F/F 0 1 nDS3 1 0 nDS2 1 BIT 0 nDRIVE SELECT 2 Active low status of the DS2 disk interface output. BIT 1 nDRIVE SELECT 3 Active low status of the DS3 disk interface output. BIT 2 WRITE GATE Active high status of the latched WGATE output signal. This bit is latched by the active going edge of WGATE and is cleared by the read of the DIR register. BIT 3 READ DATA Active high status of the latched RDATA output signal. This bit is latched by the inactive going edge of RDATA and is cleared by the read of the DIR register. BIT 4 WRITE DATA Active high status of the latched WDATA output signal. This bit is latched by the inactive going edge of WDATA and is cleared by the read of the DIR register. This bit is not gated with WGATE. BIT 5 nDRIVE SELECT 0 Active low status of the DS0 disk interface output. BIT 6 nDRIVE SELECT 1 Active low status of the DS1 disk interface output. BIT 7 nDRV2 Active low status of the DRV2 disk interface input. 22 DIGITAL OUTPUT REGISTER (DOR) Address 3F2 READ/WRITE The DOR controls the drive select and motor enables of the disk interface outputs. It also 7 MOT EN3 RESET COND. 0 6 MOT EN2 0 5 MOT EN1 0 4 MOT EN0 0 contains the enable for the DMA logic and contains a software reset bit. The contents of the DOR are unaffected by a software reset. The DOR can be written to at any time. 3 2 1 0 DMAEN nRESET DRIVE DRIVE SEL1 SEL0 0 0 0 0 BIT 0 and 1 DRIVE SELECT These two bit a are binary encoded for the four drive selects DS0-DS3, thereby allowing only one drive to be selected at one time. BIT 2 nRESET A logic "0" written to this bit resets the Floppy disk controller. This reset will remain active until a logic "1" is written to this bit. This software reset does not affect the DSR and CCR registers, nor does it affect the other bits of the DOR register. The minimum reset duration required is 100ns, therefore toggling this bit by consecutive writes to this register is a valid method of issuing a software reset. BIT 3 DMAEN PC/AT and Model 30 Mode: Writing this bit to logic "1" will enable the DRQ, nDACK, TC and FINTR outputs. This bit being a logic "0" will disable the nDACK and TC inputs, and hold the DRQ and FINTR outputs in a high impedance state. This bit is a logic "0" after a reset and in these modes. PS/2 Mode: In this mode the DRQ, nDACK, TC and FINTR pins are always enabled. During a reset, the DRQ, nDACK, TC, and FINTR pins will remain enabled, but this bit will be cleared to a logic "0". BIT 4 MOTOR ENABLE 0 This bit controls the MTR0 disk interface output. A logic "1" in this bit will cause the output pin to go active. BIT 5 MOTOR ENABLE 1 This bit controls the MTR1 disk interface output. A logic "1" in this bit will cause the output pin to go active. BIT 6 MOTOR ENABLE 2 This bit controls the MTR2 disk interface output. A logic "1" in this bit will cause the output pin to go active. BIT 7 MOTOR ENABLE 3 This bit controls the MTR3 disk interface output. A logic "1" in this bit causes the output to go active. Table 3 - Drive Activation Values DRIVE 0 1 2 3 DOR VALUE 1CH 2DH 4EH 8FH 23 TAPE DRIVE REGISTER (TDR) Address 3F3 READ/WRITE This register is included for 82077 software compatability. The robust digital data separator used in the FDC37C669 does not require its characteristics modified for tape support. The contents of this register are not used internal to the device. The TDR is unaffected by a software reset. Bits 2-7 are tri-stated when read in this mode. Table 4- Tape Select Bits DRIVE SELECTED None 1 2 3 TAPE SEL1 0 0 1 1 TAPE SEL2 0 1 0 1 Table 5 - Internal 4 Drive Decode - Normal DIGITAL OUTPUT REGISTER Bit 7 X X X 1 0 Bit 6 X X 1 X 0 Bit 5 X 1 X X 0 Bit 4 1 X X X 0 Bit1 0 0 1 1 X Bit 0 0 1 0 1 X DRIVE SELECT OUTPUTS (ACTIVE LOW) nDS3 1 1 1 0 1 nDS2 1 1 0 1 1 nDS1 1 0 1 1 1 nDS0 0 1 1 1 1 nMTR3 nBIT 7 nBIT 7 nBIT 7 nBIT 7 nBIT 7 MOTOR ON OUTPUTS (ACTIVE LOW) nMTR2 nBIT 6 nBIT 6 nBIT 6 nBIT 6 nBIT 6 nMTR1 nBIT 5 nBIT 5 nBIT 5 nBIT 5 nBIT 5 nMTR0 nBIT 4 nBIT 4 nBIT 4 nBIT 4 nBIT 4 Table 6 - Internal 4 Drive Decode - Drives 0 and 1 Swapped DIGITAL OUTPUT REGISTER Bit 7 X X X 1 0 Bit 6 X X 1 X 0 Bit 5 X 1 X X 0 Bit 4 1 X X X 0 Bit1 0 0 1 1 X Bit 0 0 1 0 1 X DRIVE SELECT OUTPUTS (ACTIVE LOW) nDS3 1 1 1 0 1 nDS2 1 1 0 1 1 nDS1 0 1 1 1 1 nDS0 1 0 1 1 1 nMTR3 nBIT 7 nBIT 7 nBIT 7 nBIT 7 nBIT 7 MOTOR ON OUTPUTS (ACTIVE LOW) nMTR2 nBIT 6 nBIT 6 nBIT 6 nBIT 6 nBIT 6 nMTR1 nBIT 4 nBIT 4 nBIT 4 nBIT 4 nBIT 4 nMTR0 nBIT 5 nBIT 5 nBIT 5 nBIT 5 nBIT 5 24 Table 7 - External 2 to 4 Drive Decode - Normal DIGITAL OUTPUT REGISTER Bit 7 X X X 1 X X X 0 Bit 6 X X 1 X X X 0 X Bit 5 X 1 X X X 0 X X Bit 4 1 X X X 0 X X X Bit1 0 0 1 1 0 0 1 1 Bit 0 0 1 0 1 0 1 0 1 DRIVE SELECT OUTPUTS (ACTIVE LOW) nDS1 0 0 1 1 0 0 1 1 nDS0 0 1 0 1 0 1 0 1 MOTOR ON OUTPUTS (ACTIVE LOW) nMTR1 1 1 1 1 1 1 1 1 nMTR0 0 0 0 0 1 1 1 1 Table 8 - External 2 to 4 Drive Decode - Drives 0 and 1 Swapped DIGITAL OUTPUT REGISTER Bit 7 X X X 1 X X X 0 Bit 6 X X 1 X X X 0 X Bit 5 X 1 X X X 0 X X Bit 4 1 X X X 0 X X X Bit1 0 0 1 1 0 0 1 1 Bit 0 0 1 0 1 0 1 0 1 DRIVE SELECT OUTPUTS (ACTIVE LOW) nDS1 0 0 1 1 0 0 1 1 nDS0 1 0 0 1 1 0 0 1 MOTOR ON OUTPUTS (ACTIVE LOW) nMTR1 1 1 1 1 1 1 1 1 nMTR0 0 0 0 0 1 1 1 1 25 Normal Floppy Mode Normal mode. Register 3F3 contains only bits 0 and 1. When this register is read, bits 2 - 7 are a high impedance. DB7 REG 3F3 Tri-state DB6 Tri-state DB5 Tri-state DB4 Tri-state DB3 Tri-state DB2 Tri-state DB1 tape sel1 DB0 tape sel0 Enhanced Floppy Mode 2 (OS2) Register 3F3 for Enhanced Floppy Mode 2 operation. DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 REG 3F3 Reserved Reserved Drive Type ID Floppy Boot Drive tape sel1 tape sel0 For this mode, DRATE0 and DRATE1 pins are inputs, and these inputs are gated into bits 6 and 7 of the 3F3 register. These two bits are not affected by a hard or soft reset. BIT 7 Reserved BIT 6 Reserved BITS 5 and 4 Drive Type ID - These Bits reflect two of the bits of configuration register 6. Which two bits depends on the last drive selected in the Digital Output Register (3F2). (See Table 11) BITS 3 and 2 Floppy Boot Drive - These bits reflect the value of configuration register 7 bits 1, 0. Bit 3 = CR7 Bit DB1. Bit 2 = CR7 Bit DB0. Bits 1 and 0 - Tape Drive Select (READ/WRITE). Same as in Normal and Enhanced Floppy Mode. 1. Table 9 - Drive Type ID Digital Output Register Register 3F3 - Drive Type ID Bit 1 0 0 1 1 Bit 0 0 1 0 1 Bit 5 CR6 - Bit 1 CR6 - Bit 3 CR6 - Bit 5 CR6 - Bit 7 Bit 4 CR6 - Bit 0 CR6 - Bit 2 CR6 - Bit 4 CR6 - Bit 6 26 DATA RATE SELECT REGISTER (DSR) Address 3F4 WRITE ONLY This register is write only. It is used to program the data rate, amount of write precompensation, power down status, and software reset. The data rate is programmed using the Configuration Control Register (CCR) not the DSR, for PC/AT and PS/2 Model 30 and 7 6 5 0 0 4 Microchannel applications. Other applications can set the data rate in the DSR. The data rate of the floppy controller is the most recent write of either the DSR or CCR. The DSR is unaffected by a software reset. A hardware reset will set the DSR to 02H, which corresponds to the default precompensation setting and 250 kbps. 3 PRECOMP1 0 2 1 0 S/W POWER RESET DOWN RESET COND. 0 0 PRECOMP2 0 PRE- DRATE DRATE COMP0 SEL1 SEL0 0 1 0 BIT 0 and 1 DATA RATE SELECT These bits control the data rate of the floppy controller. See Table 13 for the settings corresponding to the individual data rates. The data rate select bits are unaffected by a software reset, and are set to 250 kbps after a hardware reset. BIT 2 through 4 PRECOMPENSATION SELECT These three bits select the value of write precompensation that will be applied to the WDATA output signal. Table 12 shows the precompensation values for the combination of these bits settings. Track 0 is the default starting track number to start precompensation. this starting track number can be changed by the configure command. BIT 5 UNDEFINED Should be written as a logic "0". BIT 6 LOW POWER A logic "1" written to this bit will put the floppy controller into Manual Low Power mode. The floppy controller clock and data separator circuits will be turned off. The controller will come out of manual low power mode after a software reset or access to the Data Register or Main Status Register. BIT 7 SOFTWARE RESET This active high bit has the same function as the DOR RESET (DOR bit 2) except that this bit is self clearing. Table 10 - Precompensation Delays PRECOMP 432 PRECOMPENSATION DELAY 111 0.00 ns-DISABLED 001 41.67 ns 010 83.34 ns 011 125.00 ns 100 166.67 ns 101 208.33 ns 110 250.00 ns 000 Default (See Table 14) 27 DRIVE RATE DRT1 0 0 0 0 0 0 0 0 1 1 1 1 DRT0 0 0 0 0 1 1 1 1 0 0 0 0 DATA RATE SEL1 1 0 0 1 1 0 0 1 1 0 0 1 SEL0 1 0 1 0 1 0 1 0 1 0 1 0 Table 11 - Data Rates DATA RATE MFM 1Meg 500 300 250 1Meg 500 500 250 1Meg 500 2Meg 250 FM --250 150 125 --250 250 125 --250 --125 1 1 0 0 1 1 0 0 1 1 0 0 DENSEL (1) IDENT=0 0 0 1 1 0 0 1 1 0 0 1 1 DRATE (2) 1 1 0 0 1 1 0 0 1 1 0 0 1 2 1 0 1 0 1 0 1 0 1 0 1 0 IDENT=1 Drive Rate Table (Recommended) 00 = 360K, 1.2M, 720K, 1.44M and 2.88M Vertical Format 01 = 3-Mode Drive 10 = 2 Meg Tape Note 1: Note 2: This is for DENSEL in normal mode. This is for DRATE0, DRATE1 when Drive Opt are 00. Table 12 - Default Precompensation Delays PRECOMPENSATION DELAYS 125 ns 41.67 ns 125 ns 125 ns DATA RATE 2 Mbps 1 Mbps 500 Kbps 300 Kbps 250 Kbps 125 ns *The 2 Mbps data rate is only available if VCC = 5V. 28 MAIN STATUS REGISTER Address 3F4 READ ONLY The Main Status Register is a read-only register and indicates the status of the disk controller. The Main Status Register can be read at any 7 RQM 6 DIO 5 NON DMA 4 CMD BUSY time. The MSR indicates when the disk controller is ready to receive data via the Data Register. It should be read before each byte transferring to or from the data register except in DMA mode. NO delay is required when reading the MSR after a data transfer. 3 DRV3 BUSY 2 DRV2 BUSY 1 DRV1 BUSY 0 DRV0 BUSY BIT 0 - 3 DRV x BUSY These bits are set to 1s when a drive is in the seek portion of a command, including implied and overlapped seeks and recalibrates. BIT 4 COMMAND BUSY This bit is set to a 1 when a command is in progress. This bit will go active after the command byte has been accepted and goes inactive at the end of the results phase. If there is no result phase (Seek, Recalibrate commands), this bit is returned to a 0 after the last command byte. BIT 5 NON-DMA This mode is selected in the SPECIFY command and will be set to a 1 during the execution phase of a command. This is for polled data transfers and helps differentiate between the data transfer phase and the reading of result bytes. BIT 6 DIO Indicates the direction of a data transfer once a RQM is set. A 1 indicates a read and a 0 indicates a write is required. BIT 7 RQM Indicates that the host can transfer data if set to a 1. No access is permitted if set to a 0. 29 DATA REGISTER (FIFO) Address 3F5 READ/WRITE All command parameter information, disk data and result status are transferred between the host processor and the floppy disk controller through the Data Register. Data transfers are governed by the RQM and DIO bits in the Main Status Register. The Data Register defaults to FIFO disabled mode after any form of reset. This maintains PC/AT hardware compatibility. The default values can be changed through the Configure command (enable full FIFO operation with threshold control). The advantage of the FIFO is that it allows the system a larger DMA latency without causing a disk error. Table 15 gives several examples of the delays with a FIFO. The data is based upon the following formula: Threshold # x 1 DATA RATE -1.5 s = DELAY At the start of a command, the FIFO action is always disabled and command parameters must be sent based upon the RQM and DIO bit settings. As the command execution phase is entered, the FIFO is cleared of any data to ensure that invalid data is not transferred. An overrun or underrun will terminate the current command and the transfer of data. Disk writes will complete the current sector by generating a 00 pattern and valid CRC. Reads require the host to remove the remaining data so that the result phase may be entered. Table 13- FIFO Service Delay FIFO THRESHOLD MAXIMUM DELAY TO SERVICING EXAMPLES AT 2 Mbps* DATA RATE 1 byte 1 x 4 s - 1.5 s = 2.5 s 2 bytes 2 x 4 s - 1.5 s = 6.5 s 8 bytes 8 x 4 s - 1.5 s = 30.5 s 15 bytes 15 x 4 s - 1.5 s = 58.5 s FIFO THRESHOLD EXAMPLES 1 byte 2 bytes 8 bytes 15 bytes MAXIMUM DELAY TO SERVICING AT 1 Mbps DATA RATE 1 x 8 s - 1.5 s = 6.5 s 2 x 8 s - 1.5 s = 14.5 s 8 x 8 s - 1.5 s = 62.5 s 15 x 8 s - 1.5 s = 118.5 s FIFO THRESHOLD MAXIMUM DELAY TO SERVICING EXAMPLES AT 500 Kbps DATA RATE 1 byte 1 x 16 s - 1.5 s = 14.5 s 2 bytes 2 x 16 s - 1.5 s = 30.5 s 8 bytes 8 x 16 s - 1.5 s = 126.5 s 15 bytes 15 x 16 s - 1.5 s = 238.5 s *The 2 Mbps data rate is only available if VCC = 5V. 30 DIGITAL INPUT REGISTER (DIR) Address 3F7 READ ONLY This register is read-only in all modes. PC-AT Mode 7 DSK CHG RESET COND. N/A N/A N/A N/A N/A N/A N/A N/A 6 5 4 3 2 1 0 BIT 0 - 6 UNDEFINED The data bus outputs D0 - 6 will remain in a high impedance state during a read of this register. PS/2 Mode 7 DSK CHG RESET COND. N/A 6 1 N/A 5 1 N/A 4 1 N/A BIT 7 DSKCHG This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable. 3 1 N/A 2 1 0 DRATE DRATE HIGH SEL1 SEL0 DENS N/A N/A 1 BIT 0 nHIGH DENS This bit is low whenever the 500 Kbps or 1 Mbps data rates are selected, and high when 250 Kbps and 300 Kbps are selected. BITS 1 - 2 DATA RATE SELECT These bits control the data rate of the floppy controller. See Table 13 for the settings corresponding to the individual data rates. The data rate select bits are unaffected by a software reset, and are set to 250 Kbps after a hardware reset. BITS 3 - 6 UNDEFINED Always read as a logic "1" BIT 7 DSKCHG This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable. 31 Model 30 Mode 7 DSK CHG N/A 6 0 0 5 0 0 4 0 0 3 2 1 0 DMAEN NOPREC DRATE DRATE SEL1 SEL0 0 0 1 0 RESET COND. BITS 0 - 1 DATA RATE SELECT These bits control the data rate of the floppy controller. See Table 13 for the settings corresponding to the individual data rates. The data rate select bits are unaffected by a software reset, and are set to 250kb/s after a hardware reset. BIT 2 NOPREC This bit reflects the value of NOPREC bit set in the CCR register. BIT 3 DMAEN This bit reflects the value of DMAEN bit set in the DOR register bit 3. BITS 4 - 6 UNDEFINED Always read as a logic "0" BIT 7 DSKCHG This bit monitors the pin of the same name and reflects the opposite value seen on the pin. 32 CONFIGURATION CONTROL REGISTER (CCR) Address 3F7 WRITE ONLY PC/AT and PS/2 Modes 7 6 5 4 3 2 1 0 DRATE DRATE SEL1 SEL0 RESET COND. N/A N/A N/A N/A N/A N/A 1 0 BIT 0 and 1 DATA RATE SELECT 0 and 1 These bits determine the data rate of the floppy controller. See Table 13 for the appropriate values. PS/2 Model 30 Mode 7 6 5 4 BIT 2 - 7 RESERVED Should be set to a logical "0" 3 2 1 0 NOPREC DRATE DRATE SEL1 SEL0 RESET COND. N/A N/A N/A N/A N/A N/A 1 0 BIT 0 and 1 DATA RATE SELECT 0 and 1 These bits determine the data rate of the floppy controller. See Table 13 for the appropriate values. BIT 2 NO PRECOMPENSATION This bit can be set by software, but it has no functionality. It can be read by bit 2 of the DSR when in Model 30 register mode. Unaffected by software reset. BIT 3 - 7 RESERVED Should be set to a logical "0" Table 13 shows the state of the DENSEL pin. The DENSEL pin is set high after a hardware reset and is unaffected by the DOR and the DSR resets. 33 STATUS REGISTER ENCODING During the Result Phase of certain commands, the Data Register contains data bytes that give the status of the command just executed. Table 14 - Status Register 0 NAME DESCRIPTION Interrupt Code 00 - Normal termination of command. The specified command was properly executed and completed without error. 01 - Abnormal termination of command. Command execution was started, but was not successfully completed. 10 - Invalid command. The requested command could not be executed. 11 - Abnormal termination caused by Polling. The FDC completed a Seek, Relative Seek or Recalibrate command (used during a Sense Interrupt Command). The TRK0 pin failed to become a "1" after: 1. 80 step pulses in the Recalibrate command. 2. The Relative Seek command caused the FDC to step outward beyond Track 0. Unused. This bit is always "0". H DS1,0 Head Address Drive Select The current head address. The current selected drive. BIT NO. 7,6 SYMBOL IC 5 SE Seek End 4 EC Equipment Check 3 2 1,0 34 BIT NO. 7 SYMBOL EN Table 15 - Status Register 1 NAME DESCRIPTION End of Cylinder The FDC tried to access a sector beyond the final sector of the track (255D). Will be set if TC is not issued after Read or Write Data command. Unused. This bit is always "0". The FDC detected a CRC error in either the ID field or the data field of a sector. Becomes set if the FDC does not receive CPU or DMA service within the required time interval, resulting in data overrun or underrun. Unused. This bit is always "0". Any one of the following: 1. Read Data, Read Deleted Data command - the FDC did not find the specified sector. 2. Read ID command - the FDC cannot read the ID field without an error. 3. Read A Track command - the FDC cannot find the proper sector sequence. 6 5 4 DE OR Data Error Overrun/ Underrun 3 2 ND No Data 1 NW Not Writeable WP pin became a "1" while the FDC is executing a Write Data, Write Deleted Data, or Format A Track command. Missing Any one of the following: Address Mark 1. The FDC did not detect an ID address mark at the specified track after encountering the index pulse from the IDX pin twice. 2. The FDC cannot detect a data address mark or a deleted data address mark on the specified track. 0 MA 35 BIT NO. 7 6 SYMBOL CM Table 16 - Status Register 2 NAME DESCRIPTION Unused. This bit is always "0". Control Mark Any one of the following: 1. Read Data command - the FDC encountered a deleted data address mark. 2. Read Deleted Data command - the FDC encountered a data address mark. The FDC detected a CRC error in the data field. The track address from the sector ID field is different from the track address maintained inside the FDC. Unused. This bit is always "0". Unused. This bit is always "0". 5 4 3 2 1 DD WC Data Error in Data Field Wrong Cylinder BC Bad Cylinder The track address from the sector ID field is different from the track address maintained inside the FDC and is equal to FF hex, which indicates a bad track with a hard error according to the IBM soft-sectored format. 0 MD Missing Data The FDC cannot detect a data address mark or a Address Mark deleted data address mark. 36 BIT NO. 7 6 5 4 3 2 1,0 SYMBOL WP Table 17 - Status Register 3 NAME DESCRIPTION Unused. This bit is always "0". Write Protected Track 0 Head Address Drive Select Indicates the status of the WP pin. Unused. This bit is always "1". T0 HD DS1,0 Indicates the status of the TRK0 pin. Unused. This bit is always "1". Indicates the status of the HDSEL pin. Indicates the status of the DS1, DS0 pins. RESET There are three sources of system reset on the FDC: The RESET pin of the FDC37C669, a reset generated via a bit in the DOR, and a reset generated via a bit in the DSR. At power on, a Power On Reset initializes the FDC. All resets take the FDC out of the power down state. All operations are terminated upon a RESET, and the FDC enters an idle state. A reset while a disk write is in progress will corrupt the data and CRC. On exiting the reset state, various internal registers are cleared, including the Configure command information, and the FDC waits for a new command. Drive polling will start unless disabled by a new Configure command. RESET Pin (Hardware Reset) The RESET pin is a global reset and clears all registers except those programmed by the Specify command. The DOR reset bit is enabled and must be cleared by the host to exit the reset state. DOR Reset vs. DSR Reset (Software Reset) These two resets are functionally the same. Both will reset the FDC core, which affects drive status information and the FIFO circuits. The DSR reset clears itself automatically while the DOR reset requires the host to manually clear it. DOR reset has precedence over the DSR reset. The DOR reset is set automatically upon a pin reset. The user must manually clear this reset bit in the DOR to exit the reset state. MODES OF OPERATION The FDC has three modes of operation, PC/AT mode, PS/2 mode and Model 30 mode. These are determined by the state of the IDENT and MFM bits 6 and 5 respectively of configuration register 3. PC/AT mode - (IDENT high, MFM a "don't care") The PC/AT register set is enabled, the DMA enable bit of the DOR becomes valid (FINTR and DRQ can be hi Z), and TC and DENSEL become active high signals. 37 PS/2 mode - (IDENT low, MFM high) This mode supports the PS/2 models 50/60/80 configuration and register set. The DMA bit of the DOR becomes a "don't care", (FINTR and DRQ are always valid), TC and DENSEL become active low. Model 30 mode - (IDENT low, MFM low) This mode supports PS/2 Model 30 configuration and register set. The DMA enable bit of ther DOR becomes valid (FINTR and DRQ can be hi Z), TC is active high and DENSEL is active low. DMA TRANSFERS DMA transfers are enabled with the Specify command and are initiated by the FDC by activating the FDRQ pin during a data transfer command. The FIFO is enabled directly by asserting nDACK and addresses need not be valid. Note that if the DMA controller (i.e. 8237A) is programmed to function in verify mode, a pseudo read is performed by the FDC based only on nDACK. This mode is only available when the FDC has been configured into byte mode (FIFO disabled) and is programmed to do a read. With the FIFO enabled, the FDC can perform the above operation by using the new Verify command; no DMA operation is needed. CONTROLLER PHASES For simplicity, command handling in the FDC can be divided into three phases: Command, Execution, and Result. Each phase is described in the following sections. Command Phase After a reset, the FDC enters the command phase and is ready to accept a command from the host. For each of the commands, a defined set of command code bytes and parameter bytes has to be written to the FDC before the command phase is complete. (Please refer to Table 18 for the command set descriptions). These bytes of data must be transferred in the order prescribed. Before writing to the FDC, the host must examine the RQM and DIO bits of the Main Status Register. RQM and DIO must be equal to "1" and "0" respectively before command bytes may be written. RQM is set false by the FDC after each write cycle until the received byte is processed. The FDC asserts RQM again to request each parameter byte of the command unless an illegal command condition is detected. After the last parameter byte is received, RQM remains "0" and the FDC automatically enters the next phase as defined by the command definition. The FIFO is disabled during the command phase to provide for the proper handling of the "Invalid Command" condition. Execution Phase All data transfers to or from the FDC occur during the execution phase, which can proceed in DMA or non-DMA mode as indicated in the Specify command. After a reset, the FIFO is disabled. Each data byte is transferred by an FINT or FDRQ depending on the DMA mode. The Configure command can enable the FIFO and set the FIFO threshold value. The following paragraphs detail the operation of the FIFO flow control. In these descriptions, 38 A low threshold value (i.e. 2) results in longer periods of time between service requests, but requires faster servicing of the request for both read and write cases. The host reads (writes) from (to) the FIFO until empty (full), then the transfer request goes inactive. The host must be very responsive to the service request. This is the desired case for use with a "fast" system. A high value of threshold (i.e. 12) is used with a "sluggish" system by affording a long latency period after a service request, but results in more frequent service requests. Non-DMA Mode - Transfers from the FIFO to the Host The FINT pin and RQM bits in the Main Status Register are activated when the FIFO contains (16- DMA Mode - Transfers from the FIFO to the Host The FDC activates the DDRQ pin when the FIFO contains (16 - 39 If the last sector to be transferred is a partial sector, the host can stop transferring the data in mid-sector, and the FDC will continue to complete the sector as if a hardware TC was received. The only difference between these implicit functions and TC is that they return "abnormal termination" result status. Such status indications can be ignored if they were expected. Note that when the host is sending data to the FIFO of the FDC, the internal sector count will be complete when the FDC reads the last byte from its side of the FIFO. There may be a delay in the removal of the transfer request signal of up to the time taken for the FDC to read the last 16 bytes from the FIFO. The host must tolerate this delay. Result Phase The generation of FINT determines the beginning of the result phase. For each of the commands, a defined set of result bytes has to be read from the FDC before the result phase is complete. These bytes of data must be read out for another command to start. RQM and DIO must both equal "1" before the result bytes may be read. After all the result bytes have been read, the RQM and DIO bits switch to "1" and "0" respectively, and the CB bit is cleared, indicating that the FDC is ready to accept the next command. 40 COMMAND SET/DESCRIPTIONS Commands can be written whenever the FDC is in the command phase. Each command has a unique set of needed parameters and status results. The FDC checks to see that the first byte is a valid command and, if valid, proceeds with the command. If it is invalid, an interrupt is issued. The user sends a Sense Interrupt Status command which returns an invalid command error. Refer to Table 18 or explanations of the various symbols used. Table 19 lists the required parameters and the results associated with each command that the FDC is capable of performing. Table 18 - Description of Command Symbols SYMBOL C D D0, D1, D2, D3 DIR DS0, DS1 NAME Cylinder Address Data Pattern Drive Select 0-3 DESCRIPTION The currently selected address; 0 to 255. The pattern to be written in each sector data field during formatting. Designates which drives are perpendicular drives on the Perpendicular Mode Command. A "1" indicates a perpendicular drive. If this bit is 0, then the head will step out from the spindle during a relative seek. If set to a 1, the head will step in toward the spindle. DS1 0 0 1 1 DTL Special Sector Size DS0 0 1 0 1 DRIVE drive 0 drive 1 drive 2 drive 3 Direction Control Disk Drive Select By setting N to zero (00), DTL may be used to control the number of bytes transferred in disk read/write commands. The sector size (N = 0) is set to 128. If the actual sector (on the diskette) is larger than DTL, the remainder of the actual sector is read but is not passed to the host during read commands; during write commands, the remainder of the actual sector is written with all zero bytes. The CRC check code is calculated with the actual sector. When N is not zero, DTL has no meaning and should be set to FF HEX. When this bit is "1" the "DTL" parameter of the Verify command becomes SC (number of sectors per track). This active low bit when a 0, enables the FIFO. A "1" disables the FIFO (default). When set, a seek operation will be performed before executing any read or write command that requires the C parameter in the command phase. A "0" disables the implied seek. The final sector number of the current track. EC EFIFO EIS Enable Count Enable FIFO Enable Implied Seek End of Track EOT 41 Table 18 - Description of Command Symbols SYMBOL GAP GPL H/HDS HLT Gap Length Head Address Head Load Time NAME DESCRIPTION Alters Gap 2 length when using Perpendicular Mode. The Gap 3 size. (Gap 3 is the space between sectors excluding the VCO synchronization field). Selected head: 0 or 1 (disk side 0 or 1) as encoded in the sector ID field. The time interval that FDC waits after loading the head and before initializing a read or write operation. Refer to the Specify command for actual delays. The time interval from the end of the execution phase (of a read or write command) until the head is unloaded. Refer to the Specify command for actual delays. Lock defines whether EFIFO, FIFOTHR, and PRETRK parameters of the CONFIGURE COMMAND can be reset to their default values by a "Software Reset". (A reset caused by writing to the appropriate bits of either the DSR or DOR) MFM/FM Mode Selector Multi-Track Selector A one selects the double density (MFM) mode. A zero selects single density (FM) mode. When set, this flag selects the multi-track operating mode. In this mode, the FDC treats a complete cylinder under head 0 and 1 as a single track. The FDC operates as this expanded track started at the first sector under head 0 and ended at the last sector under head 1. With this flag set, a multitrack read or write operation will automatically continue to the first sector under head 1 when the FDC finishes operating on the last sector under head 0. HUT Head Unload Time LOCK MFM MT 42 Table 18 - Description of Command Symbols SYMBOL N NAME Sector Size Code DESCRIPTION This specifies the number of bytes in a sector. If this parameter is "00", then the sector size is 128 bytes. The number of bytes transferred is determined by the DTL parameter. Otherwise the sector size is (2 raised to the "N'th" power) times 128. All values up to "07" hex are allowable. "07"h would equal a sector size of 16k. It is the user's responsibility to not select combinations that are not possible with the drive. N 00 01 02 03 .. 07 NCN ND New Cylinder Number Non-DMA Mode Flag The desired cylinder number. When set to 1, indicates that the FDC is to operate in the nonDMA mode. In this mode, the host is interrupted for each data transfer. When set to 0, the FDC operates in DMA mode, interfacing to a DMA controller by means of the DRQ and nDACK signals. The bits D0-D3 of the Perpendicular Mode Command can only be modified if OW is set to 1. OW id defined in the Lock command. The current position of the head at the completion of Sense Interrupt Status command. When set, the internal polling routine is disabled. When clear, polling is enabled. Programmable from track 00 to FFH. SECTOR SIZE 128 bytes 256 bytes 512 bytes 1024 bytes ... 16 kbytes OW PCN POLL PRETRK Overwrite Present Cylinder Number Polling Disable Precompensation Start Track Number Sector Address R The sector number to be read or written. In multi-sector transfers, this parameter specifies the sector number of the first sector to be read or written. Relative cylinder offset from present cylinder as used by the Relative Seek command. RCN Relative Cylinder Number 43 Table 18 - Description of Command Symbols SYMBOL SC NAME DESCRIPTION Number of The number of sectors per track to be initialized by the Format Sectors Per Track command. The number of sectors per track to be verified during a Verify command when EC is set. Skip Flag When set to 1, sectors containing a deleted data address mark will automatically be skipped during the execution of Read Data. If Read Deleted is executed, only sectors with a deleted address mark will be accessed. When set to "0", the sector is read or written the same as the read and write commands. SK SRT Step Rate Interval The time interval between step pulses issued by the FDC. Programmable from 0.5 to 8 milliseconds in increments of 0.5 ms at the 1 Mbit data rate. Refer to the SPECIFY command for actual delays. Status 0 Status 1 Status 2 Status 3 Write Gate Alters timing of WE to allow for pre-erase loads in perpendicular drives. Registers within the FDC which store status information after a command has been executed. This status information is available to the host during the result phase after command execution. ST0 ST1 ST2 ST3 WGATE 44 INSTRUCTION SET Table 19 - Instruction Set READ DATA DATA BUS PHASE Command R/W W W W W W W W W W Execution Result R R R R R R R ST0 ST1 ST2 C H R N Sector ID information after Command execution. D7 MT 0 D6 MFM 0 D5 SK 0 D4 0 0 C H R N EOT GPL DTL Data transfer between the FDD and system. Status information after Command execution. D3 0 0 D2 1 D1 1 D0 0 REMARKS Command Codes Sector ID information prior to Command execution. HDS DS1 DS0 45 READ DELETED DATA DATA BUS PHASE Command R/W W W W W W W W W W Execution Result R R R R R R R ST0 ST1 ST2 C H R N Sector ID information after Command execution. D7 MT 0 D6 MFM 0 D5 SK 0 D4 0 0 C H R N EOT GPL DTL Data transfer between the FDD and system. Status information after Command execution. D3 1 0 D2 1 D1 0 D0 0 REMARKS Command Codes Sector ID information prior to Command execution. HDS DS1 DS0 46 WRITE DATA DATA BUS PHASE Command R/W W W W W W W W W W Execution Result R R R R R R R ST0 ST1 ST2 C H R N Sector ID information after Command execution. D7 MT 0 D6 MFM 0 D5 0 0 D4 0 0 C H R N EOT GPL DTL Data transfer between the FDD and system. Status information after Command execution. D3 0 0 D2 1 D1 0 D0 1 REMARKS Command Codes Sector ID information prior to Command execution. HDS DS1 DS0 47 WRITE DELETED DATA DATA BUS PHASE Command R/W W W W D7 0 D6 0 D5 0 0 D4 0 0 D3 1 0 C D2 0 HDS D1 0 DS1 D0 1 DS0 Sector ID information prior to Command execution. REMARKS Command Codes MT MFM W W W W W W Execution Result R R R R H R N EOT GPL DTL Data transfer between the FDD and system. ST0 ST1 ST2 C Sector ID information after Command execution. Status information after Command execution. R R R H R N 48 READ A TRACK DATA BUS PHASE Command R/W W W W D7 0 0 D6 MFM 0 D5 0 0 D4 0 0 D3 0 0 C D2 0 HDS D1 1 DS1 D0 0 DS0 Sector ID information prior to Command execution. REMARKS Command Codes W W W W W W Execution H R N EOT GPL DTL Data transfer between the FDD and system. FDC reads all of cylinders' contents from index hole to EOT. Result R R R R ST0 ST1 ST2 C Status information after Command execution. Sector ID information after Command execution. R R R H R N 49 VERIFY DATA BUS PHASE Command R/W W W W D7 EC D6 0 D5 SK 0 D4 1 0 D3 0 0 C D2 1 HDS D1 1 DS1 D0 0 DS0 Sector ID information prior to Command execution. REMARKS Command Codes MT MFM W W W W W W Execution Result R R R R H R N EOT GPL DTL/SC No data transfer takes place. ST0 ST1 ST2 C Sector ID information after Command execution. Status information after Command execution. R R R H R N VERSION DATA BUS PHASE Command Result R/W W R D7 0 1 D6 0 0 D5 0 0 D4 1 1 D3 0 0 D2 0 0 D1 0 0 D0 0 0 REMARKS Command Code Enhanced Controller 50 FORMAT A TRACK DATA BUS PHASE Command R/W W W W W W W Execution for Each Sector Repeat: W D7 0 0 D6 MFM 0 D5 0 0 D4 0 0 D3 1 0 N SC GPL D C D2 1 HDS D1 0 DS1 D0 1 DS0 Bytes/Sector Sectors/Cylinder Gap 3 Filler Byte Input Sector Parameters REMARKS Command Codes W W W H R N FDC formats an entire cylinder Result R R R R R R R ST0 ST1 ST2 Undefined Undefined Undefined Undefined Status information after Command execution 51 RECALIBRATE DATA BUS PHASE Command Execution R/W W W D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 0 0 D2 1 0 D1 1 DS1 D0 1 DS0 Head retracted to Track 0 Interrupt. SENSE INTERRUPT STATUS DATA BUS PHASE Command Result R/W W R R D7 0 D6 0 D5 0 D4 0 ST0 PCN SPECIFY DATA BUS PHASE Command R/W W W W D7 0 D6 0 D5 0 SRT HLT D4 0 D3 0 D2 0 D1 1 HUT ND D0 1 REMARKS Command Codes D3 1 D2 0 D1 0 D0 0 REMARKS Command Codes Status information at the end of each seek operation. REMARKS Command Codes 52 SENSE DRIVE STATUS DATA BUS PHASE Command Result R/W W W R D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 0 0 ST3 D2 1 HDS D1 0 DS1 D0 0 DS0 Status information about FDD REMARKS Command Codes SEEK DATA BUS PHASE Command R/W W W W Execution D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 1 0 NCN Head positioned over proper cylinder on diskette. CONFIGURE DATA BUS PHASE Command R/W W W W Execution W D7 0 0 0 D6 0 0 D5 0 0 D4 1 0 POLL PRETRK D3 0 0 D2 0 0 D1 1 0 D0 1 0 REMARKS Configure Information D2 1 HDS D1 1 DS1 D0 1 DS0 REMARKS Command Codes EIS EFIFO FIFOTHR 53 RELATIVE SEEK DATA BUS PHASE Command R/W W W W D7 1 0 D6 DIR 0 D5 0 0 D4 0 0 D3 1 0 RCN DUMPREG DATA BUS PHASE Command R/W W D7 0 D6 0 D5 0 D4 0 D3 1 D2 1 D1 1 D0 0 REMARKS *Note: Registers placed in FIFO D2 1 HDS D1 1 DS1 D0 1 DS0 REMARKS Execution Result R R R R R R R R R R LOCK 0 0 D3 EIS EFIFO SRT HLT SC/EOT D2 POLL PRETRK D1 D0 GAP FIFOTHR WGATE PCN-Drive 0 PCN-Drive 1 PCN-Drive 2 PCN-Drive 3 HUT ND 54 READ ID DATA BUS PHASE Command Execution R/W W W D7 0 0 D6 MFM 0 D5 0 0 D4 0 0 D3 1 0 D2 0 HDS D1 1 DS1 D0 0 DS0 The first correct ID information on the Cylinder is stored in Data Register R ST0 Status information after Command execution. REMARKS Commands Result Disk status after the Command has completed R R R R R R ST1 ST2 C H R N 55 PERPENDICULAR MODE DATA BUS PHASE Command R/W W D7 0 OW D6 0 0 D5 0 D3 D4 1 D2 D3 0 D1 D2 0 D0 D1 1 GAP D0 0 WGATE REMARKS Command Codes INVALID CODES DATA BUS PHASE Command R/W W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS Invalid Command Codes (No Op - FDC37C669 goes into Standby State) ST0 = 80H Invalid Codes Result R ST0 LOCK DATA BUS PHASE Command Result R/W W R D7 LOCK 0 D6 0 0 D5 0 0 D4 1 LOCK D3 0 0 D2 1 0 D1 0 0 D0 0 0 REMARKS Command Codes SC is returned if the last command that was issued was the Format command. EOT is returned if the last command was a Read or Write. NOTE: These bits are used internally only. They are not reflected in the Drive Select pins. It is the user's responsibility to maintain correspondence between these bits and the Drive Select pins (DOR). 56 DATA TRANSFER COMMANDS All of the Read Data, Write Data and Verify type commands use the same parameter bytes and return the same results information, the only difference being the coding of bits 0-4 in the first byte. An implied seek will be executed if the feature was enabled by the Configure command. This seek is completely transparent to the user. The Drive Busy bit for the drive will go active in the Main Status Register during the seek portion of the command. If the seek portion fails, it will be reflected in the results status normally returned for a Read/Write Data command. Status Register 0 (ST0) would contain the error code and C would contain the cylinder on which the seek failed. Read Data A set of nine (9) bytes is required to place the FDC in the Read Data Mode. After the Read Data command has been issued, the FDC loads the head (if it is in the unloaded state), waits the specified head settling time (defined in the Specify command), and begins reading ID Address Marks and ID fields. When the sector address read off the diskette matches with the sector address specified in the command, the FDC reads the sector's data field and transfers the data to the FIFO. After completion of the read operation from the current sector, the sector address is incremented by one and the data from the next logical sector is read and output via the FIFO. This continuous read function is called "MultiSector Read Operation". Upon receipt of TC, or an implied TC (FIFO overrun/underrun), the FDC stops sending data but will continue to read data from the current sector, check the CRC bytes, and at the end of the sector, terminate the Read Data Command. N determines the number of bytes per sector (see Table 22 below). If N is set to zero, the sector size is set to 128. The DTL value determines the number of bytes to be transferred. If DTL is less than 128, the FDC transfers the specified number of bytes to the host. For reads, it continues to read the entire 128-byte sector and checks for CRC errors. For writes, it completes the 128-byte sector by filling in zeros. If N is not set to 00 Hex, DTL should be set to FF Hex and has no impact on the number of bytes transferred. Table 20 - Sector Sizes N 00 01 02 03 .. 07 SECTOR SIZE 128 bytes 256 bytes 512 bytes 1024 bytes ... 16 Kbytes The amount of data which can be handled with a single command to the FDC depends upon MT (multi-track) and N (number of bytes/sector). The Multi-Track function (MT) allows the FDC to read data from both sides of the diskette. For a particular cylinder, data will be transferred starting at Sector 1, Side 0 and completing the last sector of the same track at Side 1. If the host terminates a read or write operation in the FDC, the ID information in the result phase is dependent upon the state of the MT bit and EOT byte. Refer to Table 23. At the completion of the Read Data command, the head is not unloaded until after the Head Unload Time Interval (specified in the Specify command) has elapsed. If the host issues another command before the head unloads, then the head settling time may be saved between subsequent reads. 57 If the FDC detects a pulse on the nINDEX pin twice without finding the specified sector (meaning that the diskette's index hole passes through index detect logic in the drive twice), the FDC sets the IC code in Status Register 0 to "01" indicating abnormal termination, sets the ND bit in Status Register 1 to "1" indicating a sector not found, and terminates the Read Data Command. After reading the ID and Data Fields in each sector, the FDC checks the CRC bytes. If a CRC error occurs in the ID or data field, the FDC sets the IC code in Status Register 0 to "01" indicating abnormal termination, sets the DE bit flag in Status Register 1 to "1", sets the DD bit in Status Register 2 to "1" if CRC is incorrect in the ID field, and terminates the Read Data Command. Table 22 describes the effect of the SK bit on the Read Data command execution and results. Except where noted in Table 22, the C or R value of the sector address is automatically incremented (see Table 24). MT 0 1 0 1 0 1 N 1 1 2 2 3 3 Table 21 - Effects of MT and N Bits MAXIMUM TRANSFER FINAL SECTOR READ CAPACITY FROM DISK 256 x 26 = 6,656 256 x 52 = 13,312 512 x 15 = 7,680 512 x 30 = 15,360 1024 x 8 = 8,192 1024 x 16 = 16,384 26 at side 0 or 1 26 at side 1 15 at side 0 or 1 15 at side 1 8 at side 0 or 1 16 at side 1 SK BIT VALUE Table 22 - Skip Bit vs Read Data Command DATA ADDRESS MARK TYPE RESULTS ENCOUNTERED SECTOR CM BIT OF DESCRIPTION READ? ST2 SET? OF RESULTS Normal Data Deleted Data Yes Yes No Yes Normal termination. Address not incremented. Next sector not searched for. Normal termination. Normal termination. Sector not read ("skipped"). 0 0 1 1 Normal Data Deleted Data Yes No No Yes 58 Read Deleted Data This command is the same as the Read Data command, only it operates on sectors that contain a Deleted Data Address Mark at the beginning of a Data Field. Table 25 describes the effect of the SK bit on the Read Deleted Data command execution and results. Except where noted in Table 25, the C or R value of the sector address is automatically incremented (see Table 26). SK BIT VALUE 0 0 1 1 Table 23 - Skip Bit vs. Read Deleted Data Command RESULTS DATA ADDRESS MARK TYPE SECTOR CM BIT OF DESCRIPTION ENCOUNTERED READ? ST2 SET? OF RESULTS Normal Data Yes Yes Address not incremented. Next sector not searched for. Normal Deleted Data Yes No termination. Normal Normal Data No Yes termination. Sector not read ("skipped"). Normal Deleted Data Yes No termination. and sets the ND flag of Status Register 1 to a "1" if there is no comparison. Multi-track or skip operations are not allowed with this command. The MT and SK bits (bits D7 and D5 of the first command byte respectively) should always be set to "0". This command terminates when the EOT specified number of sectors has not been read. If the FDC does not find an ID Address Mark on the diskette after the second occurrence of a pulse on the IDX pin, then it sets the IC code in Status Register 0 to "01" (abnormal termination), sets the MA bit in Status Register 1 to "1", and terminates the command. Read A Track This command is similar to the Read Data command except that the entire data field is read continuously from each of the sectors of a track. Immediately after encountering a pulse on the nINDEX pin, the FDC starts to read all data fields on the track as continuous blocks of data without regard to logical sector numbers. If the FDC finds an error in the ID or DATA CRC check bytes, it continues to read data from the track and sets the appropriate error bits at the end of the command. The FDC compares the ID information read from each sector with the specified value in the command 59 MT HEAD 0 Table 24 - Result Phase Table FINAL SECTOR ID INFORMATION AT RESULT PHASE TRANSFERRED TO HOST C H R N Less than EOT Equal to EOT Less than EOT Equal to EOT Less than EOT Equal to EOT Less than EOT Equal to EOT NC C+1 NC C+1 NC NC NC C+1 NC NC NC NC NC LSB NC LSB R+1 01 R+1 01 R+1 01 R+1 01 NC NC NC NC NC NC NC NC 0 1 0 1 1 NC: No Change, the same value as the one at the beginning of command execution. LSB: Least Significant Bit, the LSB of H is complemented. Write Data After the Write Data command has been issued, the FDC loads the head (if it is in the unloaded state), waits the specified head load time if unloaded (defined in the Specify command), and begins reading ID fields. When the sector address read from the diskette matches the sector address specified in the command, the FDC reads the data from the host via the FIFO and writes it to the sector's data field. After writing data into the current sector, the FDC computes the CRC value and writes it into the CRC field at the end of the sector transfer. The Sector Number stored in "R" is incremented by one, and the FDC continues writing to the next data field. The FDC continues this "MultiSector Write Operation". Upon receipt of a terminal count signal or if a FIFO over/under run occurs while a data field is being written, then the remainder of the data field is filled with zeros. The FDC reads the ID field of each sector and checks the CRC bytes. If it detects a CRC error in one of the ID fields, it sets the IC code in Status Register 0 to "01" (abnormal termination), sets the DE bit of Status Register 1 to "1", and terminates the Write Data command. The Write Data command operates in much the same manner as the Read Data command. The following items are the same. Please refer to the Read Data Command for details: ! ! ! ! ! Transfer Capacity EN (End of Cylinder) bit ND (No Data) bit Head Load, Unload Time Interval ID information when the host terminates the command ! Definition of DTL when N = 0 and when N does not = 0 Write Deleted Data This command is almost the same as the Write Data command except that a Deleted Data Address Mark is written at the beginning of the Data Field instead of the normal Data Address Mark. This command is typically used to mark a bad sector containing an error on the floppy disk. 60 Verify The Verify command is used to verify the data stored on a disk. This command acts exactly like a Read Data command except that no data is transferred to the host. Data is read from the disk and CRC is computed and checked against the previously-stored value. Because data is not transferred to the host, TC (pin 25) cannot be used to terminate this command. By setting the EC bit to "1", an implicit TC will be issued to the FDC. This implicit TC will occur when the SC value has decremented to 0 (an SC value of 0 will verify 256 sectors). This command can also be terminated by setting the EC bit to "0" and the EOT value equal to the final sector to be checked. If EC is set to "0", DTL/SC should be programmed to 0FFH. Refer to Table 26 and Table 27 for information concerning the values of MT and EC versus SC and EOT value. Definitions: # Sectors Per Side = Number of formatted sectors per each side of the disk. # Sectors Remaining = Number of formatted sectors left which can be read, including side 1 of the disk if MT is set to "1". MT 0 0 0 0 1 1 1 1 EC 0 0 1 1 0 0 1 1 Table 25 - Verify Command Result Phase Table SC/EOT VALUE TERMINATION RESULT SC = DTL EOT < # Sectors Per Side SC = DTL EOT > # Sectors Per Side SC < # Sectors Remaining AND EOT < # Sectors Per Side SC > # Sectors Remaining OR EOT > # Sectors Per Side SC = DTL EOT < # Sectors Per Side SC = DTL EOT > # Sectors Per Side SC < # Sectors Remaining AND EOT < # Sectors Per Side SC > # Sectors Remaining OR EOT > # Sectors Per Side Success Termination Result Phase Valid Unsuccessful Termination Result Phase Invalid Successful Termination Result Phase Valid Unsuccessful Termination Result Phase Invalid Successful Termination Result Phase Valid Unsuccessful Termination Result Phase Invalid Successful Termination Result Phase Valid Unsuccessful Termination Result Phase Invalid NOTE: If MT is set to "1" and the SC value is greater than the number of remaining formatted sectors on Side 0, verifying will continue on Side 1 of the disk. 61 Format A Track The Format command allows an entire track to be formatted. After a pulse from the IDX pin is detected, the FDC starts writing data on the disk including gaps, address marks, ID fields, and data fields per the IBM System 34 or 3740 format (MFM or FM respectively). The particular values that will be written to the gap and data field are controlled by the values programmed into N, SC, GPL, and D which are specified by the host during the command phase. The data field of the sector is filled with the data byte specified by D. The ID field for each sector is supplied by the host; that is, four data bytes per sector are needed by the FDC for C, H, R, and N (cylinder, head, sector number and sector size respectively). After formatting each sector, the host must send new values for C, H, R and N to the FDC for the next sector on the track. The R value (sector number) is the only value that must be changed by the host after each sector is formatted. This allows the disk to be formatted with nonsequential sector addresses (interleaving). This incrementing and formatting continues for the whole track until the FDC encounters a pulse on the IDX pin again and it terminates the command. Table 28 contains typical values for gap fields which are dependent upon the size of the sector and the number of sectors on each track. Actual values can vary due to drive electronics. FORMAT FIELDS SYSTEM 34 (DOUBLE DENSITY) FORMAT GAP4a 80x 4E SYNC 12x 00 IAM GAP1 SYNC 50x 12x 4E 00 IDAM C Y L H D S E C N O C GAP2 SYNC R 22x 12x C 4E 00 DATA AM DATA 3x FB A1 F8 C R C GAP3 GAP 4b 3x FC C2 3x FE A1 SYSTEM 3740 (SINGLE DENSITY) FORMAT GAP4a 40x FF SYNC 6x 00 IAM GAP1 SYNC 26x 6x FF 00 IDAM C Y L H D S E C N O C GAP2 SYNC R 11x 6x C FF 00 DATA AM DATA FB or F8 C R C GAP3 GAP 4b FC FE PERPENDICULAR FORMAT GAP4a 80x 4E SYNC 12x 00 IAM GAP1 SYNC 50x 12x 4E 00 IDAM C Y L H D S E C N O C GAP2 SYNC R 41x 12x C 4E 00 DATA AM DATA 3x FB A1 F8 C R C GAP3 GAP 4b 3x FC C2 3x FE A1 62 FORMAT Table 26 - Typical Values for Formatting SECTOR SIZE N SC GPL1 128 128 512 1024 2048 4096 ... 256 256 512* 1024 2048 4096 ... 128 256 512 256 512** 1024 00 00 02 03 04 05 ... 01 01 02 03 04 05 ... 0 1 2 1 2 3 12 10 08 04 02 01 12 10 09 04 02 01 0F 09 05 0F 09 05 07 10 18 46 C8 C8 0A 20 2A 80 C8 C8 07 0F 1B 0E 1B 35 GPL2 09 19 30 87 FF FF 0C 32 50 F0 FF FF 1B 2A 3A 36 54 74 FM 5.25" Drives MFM 3.5" Drives FM MFM GPL1 = suggested GPL values in Read and Write commands to avoid splice point between data field and ID field of contiguous sections. GPL2 = suggested GPL value in Format A Track command. *PC/AT values (typical) **PS/2 values (typical). Applies with 1.0 MB and 2.0 MB drives. NOTE: All values except sector size are in hex. 63 CONTROL COMMANDS Control commands differ from the other commands in that no data transfer takes place. Three commands generate an interrupt when complete: Read ID, Recalibrate, and Seek. The other control commands do not generate an interrupt. Read ID The Read ID command is used to find the present position of the recording heads. The FDC stores the values from the first ID field it is able to read into its registers. If the FDC does not find an ID address mark on the diskette after the second occurrence of a pulse on the nINDEX pin, it then sets the IC code in Status Register 0 to "01" (abnormal termination), sets the MA bit in Status Register 1 to "1", and terminates the command. The following commands will generate an interrupt upon completion. They do not return any result bytes. It is highly recommended that control commands be followed by the Sense Interrupt Status command. Otherwise, valuable interrupt status information will be lost. Recalibrate This command causes the read/write head within the FDC to retract to the track 0 position. The FDC clears the contents of the PCN counter and checks the status of the nTR0 pin from the FDD. As long as the nTR0 pin is low, the DIR pin remains 0 and step pulses are issued. When the nTR0 pin goes high, the SE bit in Status Register 0 is set to "1" and the command is terminated. If the nTR0 pin is still low after 79 step pulses have been issued, the FDC sets the SE and the EC bits of Status Register 0 to "1" and terminates the command. Disks capable of handling more than 80 tracks per side may require more than one Recalibrate command to return the head back to physical Track 0. The Recalibrate command does not have a result phase. The Sense Interrupt Status command must be issued after the Recalibrate command to effectively terminate it and to provide verification of the head position (PCN). During the command phase of the recalibrate operation, the FDC is in the BUSY state, but during the execution phase it is in a NON-BUSY state. At this time, another Recalibrate command may be issued, and in this manner parallel Recalibrate operations may be done on up to four drives at once. Upon power up, the software must issue a Recalibrate command to properly initialize all drives and the controller. Seek The read/write head within the drive is moved from track to track under the control of the Seek command. The FDC compares the PCN, which is the current head position, with the NCN and performs the following operation if there is a difference: PCN < NCN: Direction signal to drive set to "1" (step in) and issues step pulses. PCN > NCN: Direction signal to drive set to "0" (step out) and issues step pulses. The rate at which step pulses are issued is controlled by SRT (Stepping Rate Time) in the Specify command. After each step pulse is issued, NCN is compared against PCN, and when NCN = PCN the SE bit in Status Register 0 is set to "1" and the command is terminated. During the command phase of the seek or recalibrate operation, the FDC is in the BUSY state, but during the execution phase it is in the NON-BUSY state. At this time, another Seek or Recalibrate command may be issued, and in this manner, parallel seek operations may be done on up to four drives at once. 64 Note that if implied seek is not enabled, the read and write commands should be preceded by: 1) Seek command - Step to the proper track 2) Sense Interrupt Status command Terminate the Seek command 3) Read ID - Verify head is on proper track 4) Issue Read/Write command. Table 27 - Interrupt Identification SE 0 1 IC 11 00 INTERRUPT DUE TO Polling Normal termination of Seek or Recalibrate command Abnormal termination of Seek or Recalibrate command - 1 01 The Seek command does not have a result phase. Therefore, it is highly recommended that the Sense Interrupt Status command be issued after the Seek command to terminate it and to provide verification of the head position (PCN). The H bit (Head Address) in ST0 will always return to a "0". When exiting POWERDOWN mode, the FDC clears the PCN value and the status information to zero. Prior to issuing the POWERDOWN command, it is highly recommended that the user service all pending interrupts through the Sense Interrupt Status command. Sense Interrupt Status An interrupt signal on FINT pin is generated by the FDC for one of the following reasons: 1. Upon entering the Result Phase of: a. Read Data command b. Read A Track command c. Read ID command d. Read Deleted Data command e. Write Data command f. Format A Track command g. Write Deleted Data command h. Verify command 2. End of Seek, Relative Seek, or Recalibrate command 3. FDC requires a data transfer during the execution phase in the non-DMA mode The Sense Interrupt Status command resets the interrupt signal and, via the IC code and SE bit of Status Register 0, identifies the cause of the interrupt. The Seek, Relative Seek, and Recalibrate commands have no result phase. The Sense Interrupt Status command must be issued immediately after these commands to terminate them and to provide verification of the head position (PCN). The H (Head Address) bit in ST0 will always return a "0". If a Sense Interrupt Status is not issued, the drive will continue to be BUSY and may affect the operation of the next command. Sense Drive Status Sense Drive Status obtains drive status information. It has not execution phase and goes directly to the result phase from the command phase. Status Register 3 contains the drive status information. Specify The Specify command sets the initial values for each of the three internal times. The HUT (Head Unload Time) defines the time from the end of the execution phase of one of the read/write commands to the head unload state. The SRT (Step Rate Time) defines the time interval between adjacent step pulses. Note that the spacing between the first and second step pulses may be shorter than the remaining step pulses. The HLT (Head Load Time) defines the time between when the Head Load signal goes high and the read/write operation starts. 65 The values change with the data rate speed selection and are documented in Table 30. The values are the same for MFM and FM. Table 28 - Drive Control Delays (ms) HUT 2M 0 1 .. E F 64 4 .. 56 60 1M 128 8 .. 112 120 500K 256 16 .. 224 240 300K 426 26.7 .. 373 400 250K 512 32 .. 448 480 2M 4 3.75 .. 0.5 0.25 HLT 2M 00 01 02 .. 7F 7F 64 0.5 1 .. 63 63.5 1M 128 1 2 .. 126 127 500K 256 2 4 .. 252 254 300K 426 3.3 6.7 .. 420 423 1M 8 7.5 .. 1 0.5 16 15 .. 2 1 SRT 500K 300K 26.7 25 .. 3.33 1.67 250K 32 30 .. 4 2 250K 512 4 8 . 504 508 The choice of DMA or non-DMA operations is made by the ND bit. When this bit is "1", the non-DMA mode is selected, and when ND is "0", the DMA mode is selected. In DMA mode, data transfers are signaled by the FDRQ pin. NonDMA mode uses the RQM bit and the FINT pin to signal data transfers. Configure The Configure command is issued to select the special features of the FDC. A Configure command need not be issued if the default values of the FDC meet the system requirements. Configure Default Values: EIS - No Implied Seeks EFIFO - FIFO Disabled POLL - Polling Enabled FIFOTHR - FIFO Threshold Set to 1 Byte PRETRK - Pre-Compensation Set to Track 0 EIS - Enable Implied Seek. When set to "1", the FDC will perform a Seek operation before executing a read or write command. Defaults to no implied seek. EFIFO - A "1" disables the FIFO (default). This means data transfers are asked for on a byteby-byte basis. Defaults to "1", FIFO disabled. The threshold defaults to "1". POLL - Disable polling of the drives. Defaults to "0", polling enabled. When enabled, a single interrupt is generated after a reset. No polling is performed while the drive head is loaded and the head unload delay has not expired. FIFOTHR - The FIFO threshold in the execution phase of read or write commands. This is programmable from 1 to 16 bytes. Defaults to one byte. A "00" selects one byte; "0F" selects 16 bytes. 66 PRETRK - Pre-Compensation Start Track Number. Programmable from track 0 to 255. Defaults to track 0. A "00" selects track 0; "FF" selects track 255. Version The Version command checks to see if the controller is an enhanced type or the older type (765A). A value of 90 H is returned as the result byte. Relative Seek The command is coded the same as for Seek, except for the MSB of the first byte and the DIR bit. DIR Head Step Direction Control DIR 0 1 RCN ACTION Step Head Out Step Head In issued, the FDC will move the head the specified number of tracks, regardless of the internal cylinder position register (but will increment the register). If the head was on track 40 (d), the maximum track that the FDC could position the head on using Relative Seek will be 295 (D), the initial track + 255 (D). The maximum count that the head can be moved with a single Relative Seek command is 255 (D). The internal register, PCN, will overflow as the cylinder number crosses track 255 and will contain 39 (D). The resulting PCN value is thus (RCN + PCN) mod 256. Functionally, the FDC starts counting from 0 again as the track number goes above 255 (D). It is the user's responsibility to compensate FDC functions (precompensation track number) when accessing tracks greater than 255. The FDC does not keep track that it is working in an "extended track area" (greater than 255). Any command issued will use the current PCN value except for the Recalibrate command, which only looks for the TRACK0 signal. Recalibrate will return an error if the head is farther than 79 due to its limitation of issuing a maximum of 80 step pulses. The user simply needs to issue a second Recalibrate command. The Seek command and implied seeks will function correctly within the 44 (D) track (299-255) area of the "extended track area". It is the user's responsibility not to issue a new track position that will exceed the maximum track that is present in the extended area. To return to the standard floppy range (0-255) of tracks, a Relative Seek should be issued to cross the track 255 boundary. A Relative Seek can be used instead of the normal Seek, but the host is required to calculate the difference between the current head location and the new (target) head location. This may require the host to issue a Read ID command to ensure that the head is physically on the track that software assumes it to be. Different FDC commands will return different cylinder results which may be difficult 67 Relative Cylinder Number that determines how many tracks to step the head in or out from the current track number. The Relative Seek command differs from the Seek command in that it steps the head the absolute number of tracks specified in the command instead of making a comparison against an internal register. The Seek command is good for drives that support a maximum of 256 tracks. Relative Seeks cannot be overlapped with other Relative Seeks. Only one Relative Seek can be active at a time. Relative Seeks may be overlapped with Seeks and Recalibrates. Bit 4 of Status Register 0 (EC) will be set if Relative Seek attempts to step outward beyond Track 0. As an example, assume that a floppy drive has 300 useable tracks. The host needs to read track 300 and the head is on any track (0-255). If a Seek command is issued, the head will stop at track 255. If a Relative Seek command is to keep track of with software without the Read ID command. Perpendicular Mode The Perpendicular Mode command should be issued prior to executing Read/Write/Format commands that access a disk drive with perpendicular recording capability. With this command, the length of the Gap2 field and VCO enable timing can be altered to accommodate the unique requirements of these drives. Table 31 describes the effects of the WGATE and GAP bits for the Perpendicular Mode command. Upon a reset, the FDC will default to the conventional mode (WGATE = 0, GAP = 0). Selection of the 500 Kbps and 1 Mbps perpendicular modes is independent of the actual data rate selected in the Data Rate Select Register. The user must ensure that these two data rates remain consistent. The Gap2 and VCO timing requirements for perpendicular recording type drives are dictated by the design of the read/write head. In the design of this head, a pre-erase head precedes the normal read/write head by a distance of 200 micrometers. This works out to about 38 bytes at a 1 Mbps recording density. Whenever the write head is enabled by the Write Gate signal, the pre-erase head is also activated at the same time. Thus, when the write head is initially turned on, flux transitions recorded on the media for the first 38 bytes will not be preconditioned with the pre-erase head since it has not yet been activated. To accommodate this head activation and deactivation time, the Gap2 field is expanded to a length of 41 bytes. The format field shown on page 61 illustrates the change in the Gap2 field size for the perpendicular format. On the read back by the FDC, the controller must begin synchronization at the beginning of the sync field. For the conventional mode, the internal PLL VCO is enabled (VCOEN) approximately 24 bytes from the start of the Gap2 field. But, when the controller operates in the 1 Mbps perpendicular mode (WGATE = 1, GAP = 1), VCOEN goes active after 43 bytes to accommodate the increased Gap2 field size. For both cases, and approximate two-byte cushion is maintained from the beginning of the sync field for the purposes of avoiding write splices in the presence of motor speed variation. For the Write Data case, the FDC activates Write Gate at the beginning of the sync field under the conventional mode. The controller then writes a new sync field, data address mark, data field, and CRC as shown in Figure 4. With the pre-erase head of the perpendicular drive, the write head must be activated in the Gap2 field to insure a proper write of the new sync field. For the 1 Mbps perpendicular mode (WGATE = 1, GAP = 1), 38 bytes will be written in the Gap2 space. Since the bit density is proportional to the data rate, 19 bytes will be written in the Gap2 field for the 500 Kbps perpendicular mode (WGATE = 1, GAP =0). It should be noted that none of the alterations in Gap2 size, VCO timing, or Write Gate timing affect normal program flow. The information provided here is just for background purposes and is not needed for normal operation. Once the Perpendicular Mode command is invoked, FDC software behavior from the user standpoint is unchanged. The perpendicular mode command is enhanced to allow specific drives to be designated Perpendicular recording drives. This enhancement allows data transfers between Conventional and Perpendicular drives without having to issue Perpendicular mode commands between the accesses of the different drive types, nor having to change write precompensation values. 68 When both GAP and WGATE bits of the PERPENDICULAR MODE COMMAND are both programmed to "0" (Conventional mode), then D0, D1, D2, D3, and D4 can be programmed independently to "1" for that drive to be set automatically to Perpendicular mode. In this mode the following set of conditions also apply: 1. The GAP2 written to a perpendicular drive during a write operation will depend upon the programmed data rate. 2. The write pre-compensation given to a perpendicular mode drive wil be 0ns. 3. For D0-D3 programmed to "0" for conventional mode drives any data written will be at the currently programmed write pre-compensation. Note: Bits D0-D3 can only be overwritten when OW is programmed as a "1". If either GAP or WGATE is a "1" then D0-D3 are ignored. Software and hardware resets have the following effect on the PERPENDICULAR MODE COMMAND: 1. "Software" resets (via the DOR or DSR registers) will only clear GAP and WGATE bits to "0". D0-D3 are unaffected and retain their previous value. 2. "Hardware" resets will clear all bits (GAP, WGATE and D0-D3) to "0", i.e all conventional mode. WGATE 0 0 1 1 Table 29 - Effects of WGATE and GAP Bits PORTION OF GAP 2 WRITTEN BY LENGTH OF GAP2 FORMAT WRITE DATA OPERATION GAP MODE FIELD 0 1 0 1 Conventional Perpendicular (500 Kbps) Reserved (Conventional) Perpendicular (1 Mbps) 22 Bytes 22 Bytes 22 Bytes 41 Bytes 0 Bytes 19 Bytes 0 Bytes 38 Bytes LOCK In order to protect systems with long DMA latencies against older application software that can disable the FIFO the LOCK Command has been added. This command should only be used by the FDC routines, and application software should refrain from using it. If an application calls for the FIFO to be disabled then the CONFIGURE command should be used. The LOCK command defines whether the EFIFO, FIFOTHR, and PRETRK parameters of the CONFIGURE command can be RESET by the DOR and DSR registers. When the LOCK bit is set to logic "1" all subsequent "software RESETS by the DOR and DSR registers will not change the previously set parameters to their default values. All "hardware" RESET from the RESET pin will set the LOCK bit to logic "0" and return the EFIFO, FIFOTHR, and PRETRK to 69 their default values. A status byte is returned immediately after issuing a LOCK command. This byte reflects the value of the LOCK bit set by the command byte. ENHANCED DUMPREG The DUMPREG command is designed to support system run-time diagnostics and application software development and debug. To accommodate the LOCK command and the enhanced PERPENDICULAR MODE command the eighth byte of the DUMPREG command has been modified to contain the additional data from these two commands. COMPATIBILITY The FDC37C669 was designed with software compatibility in mind. It is a fully backwardscompatible solution with the older generation 765A/B disk controllers. The FDC also implements on-board registers for compatibility with the PS/2, as well as PC/AT and PC/XT, floppy disk controller subsystems. After a hardware reset of the FDC, all registers, functions and enhancements default to a PC/AT, PS/2 or PS/2 Model 30 compatible operating mode, depending on how the IDENT and MFM bits are configured by the system bios. 70 PARALLEL PORT FLOPPY DISK CONTROLLER In this mode, the Floppy Disk Control signals are available on the parallel port pins. When this mode is selected, the parallel port is not available. There are two modes of operation, PPFD1 and PPFD2. These modes can be selected in Configuration Register 4. PPFD1 has only drive 1 on the parallel port pins; PPFD2 has drive 0 and 1 on the parallel port pins. PPFD1: Drive 0 is on the FDC pins Drive 1 is on the Parallel port pins PPFD2: Drive 0 is on the Parallel port pins Drive 1 is on the Parallel port pins When the PPFDC is selected the following pins are set as follows: 1. 2. nDACK: Assigned to the parallel port device during configuration. PDRQ (assigned to the parallel port): not ECP = high-Z, ECP & dmaEn = 0, ECP & not dmaEn = high-Z IRQ assigned to the parallel port: not active, this is hi-Z or Low depending on settings. The following parallel port pins are read as follows by a read of the parallel port register: 1. 2. Data Register (read) = last Data Register (write) Control Register are read as "cable not connected" STROBE, AUTOFD and SLC = 0 and nINIT = 1; Status Register reads: nBUSY = 0, PE = 0, SLCT = 0, nACK = 1, nERR = 1. 3. The following FDC pins are all in the high impedence state when the PPFDC is actually selected by the drive select register: 1. nWDATA, DENSEL, nHDSEL, nWGATE, nDIR, nSTEP, nDS1, nDS0, nMTRO, nMTR1. If PPFDx is selected, then the parallel port can not be used as a parallel port until "Normal" mode is selected. 2. 3. The FDC signals are muxed onto the Parallel Port pins as shown in Table 32. 71 Table 30 - FDC Parallel Port Pins CONNECTOR PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CHIP PIN # 77 71 70 69 68 66 65 64 63 62 61 60 59 76 75 74 73 SPP MODE nSTB PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 nACK BUSY PE SLCT nAFD nERR nINIT nSLIN PIN DIRECTION I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I I/O I I/O I/O FDC MODE (nDS0) nINDEX nTRKO nWP nRDATA nDSKCHG nMEDIA_ID0 (nMTR0) nMEDIA_ID1 nDS1 nMTR1 nWDATA nWGATE nDENSEL nHDSEL nDIR nSTEP PIN DIRECTION I/(0) I I I I I I I/(0) I 0 0 0 0 0 0 0 0 These pins are outputs in mode PPFD2. Inputs in mode PPFD1 72 SERIAL PORT (UART) The FDC37C669 incorporates two full function UARTs. They are compatible with the NS16450, the 16450 ACE registers and the NS16550A. The UARTs perform serial-toparallel conversion on received characters and parallel-to-serial conversion on transmit characters. The data rates are independently programmable from 115.2K baud down to 50 baud. The character options are programmable for 1 start; 1, 1.5 or 2 stop bits; even, odd, sticky or no parity; and prioritized interrupts. The UARTs each contain a programmable baud rate generator that is capable of dividing the input clock or crystal by a number from 1 to 65535. The UARTs are also capable of supporting the MIDI data rate. Refer to the FDC37C669 Configuration Registers for information on disabling, power down and changing the base address of the UARTs. The interrupt from a UART is enabled by programming OUT2 of that UART to a logic "1". OUT2 being a logic "0" disables that UART's interrupt. REGISTER DESCRIPTION Addressing of the accessible registers of the Serial Port is shown below. The base addresses of the serial ports are defined by the configuration registers (see Configuration section). The Serial Port registers are located at sequentially increasing addresses above these base addresses. The FDC37C669 contains two serial ports, each of which contain a register set as described below. DLAB* 0 0 0 X X X X X X X 1 1 A2 0 0 0 0 0 0 1 1 1 1 0 0 Table 31 - Addressing the Serial Port A1 A0 REGISTER NAME 0 0 0 1 1 1 0 0 1 1 0 0 0 0 1 0 0 1 0 1 0 1 0 1 Receive Buffer (read) Transmit Buffer (write) Interrupt Enable (read/write) Interrupt Identification (read) FIFO Control (write) Line Control (read/write) Modem Control (read/write) Line Status (read/write) Modem Status (read/write) Scratchpad (read/write) Divisor LSB (read/write) Divisor MSB (read/write) *NOTE: DLAB is Bit 7 of the Line Control Register 73 The following section describes the operation of the registers. RECEIVE BUFFER REGISTER (RB) Address Offset = 0H, DLAB = 0, READ ONLY This register holds the received incoming data byte. Bit 0 is the least significant bit, which is transmitted and received first. Received data is double buffered; this uses an additional shift register to receive the serial data stream and convert it to a parallel 8 bit word which is transferred to the Receive Buffer register. The shift register is not accessible. TRANSMIT BUFFER REGISTER (TB) Address Offset = 0H, DLAB = 0, WRITE ONLY Bit 1 This bit enables the Transmitter Holding Register Empty Interrupt when set to logic "1". Bit 2 This bit enables the Received Line Status Interrupt when set to logic "1". The error sources causing the interrupt are Overrun, Parity, Framing and Break. The Line Status Register must be read to determine the source. Bit 3 This bit enables the MODEM Status Interrupt when set to logic "1". This is caused when one of the Modem Status Register bits changes state. Bits 4 through 7 These bits are always logic "0". FIFO CONTROL REGISTER (FCR) Address Offset = 2H, DLAB = X, WRITE This is a write only register at the same location as the IIR. This register is used to enable and clear the FIFOs, set the RCVR FIFO trigger level. Note: DMA is not supported. Bit 0 Setting this bit to a logic "1" enables both the XMIT and RCVR FIFOs. Clearing this bit to a logic "0" disables both the XMIT and RCVR FIFOs and clears all bytes from both FIFOs. When changing from FIFO Mode to non-FIFO (16450) mode, data is automatically cleared from the FIFOs. This bit must be a 1 when other bits in this register are written to or they will not be properly programmed. Bit 1 Setting this bit to a logic "1" clears all bytes in the RCVR FIFO and resets its counter logic to 0. The shift register is not cleared. This bit is selfclearing. This register contains the data byte to be transmitted. The transmit buffer is double buffered, utilizing an additional shift register (not accessible) to convert the 8 bit data word to a serial format. This shift register is loaded from the Transmit Buffer when the transmission of the previous byte is complete. INTERRUPT ENABLE REGISTER (IER) Address Offset = 1H, DLAB = 0, READ/WRITE The lower four bits of this register control the enables of the five interrupt sources of the Serial Port interrupt. It is possible to totally disable the interrupt system by resetting bits 0 through 3 of this register. Similarly, setting the appropriate bits of this register to a high, selected interrupts can be enabled. Disabling the interrupt system inhibits the Interrupt Identification Register and disables any Serial Port interrupt out of the FDC37C669. All other system functions operate in their normal manner, including the Line Status and MODEM Status Registers. The contents of the Interrupt Enable Register are described below. Bit 0 This bit enables the Received Data Available Interrupt (and timeout interrupts in the FIFO mode) when set to logic "1". 74 Bit 2 Setting this bit to a logic "1" clears all bytes in the XMIT FIFO and resets its counter logic to 0. The shift register is not cleared. This bit is selfclearing. Bit 3 Writing to this bit has no effect on the operation of the UART. The RXRDY and TXRDY pins are not available on this chip. Bit 4,5 Reserved Bit 6,7 These bits are used to set the trigger level for the RCVR FIFO interrupt. 3. Transmitter Holding Register Empty 4. MODEM Status (lowest priority) Information indicating that a prioritized interrupt is pending and the source of that interrupt is stored in the Interrupt Identification Register (refer to Interrupt Control Table). When the CPU accesses the IIR, the Serial Port freezes all interrupts and indicates the highest priority pending interrupt to the CPU. During this CPU access, even if the Serial Port records new interrupts, the current indication does not change until access is completed. The contents of the IIR are described below. Bit 0 This bit can be used in either a hardwired prioritized or polled environment to indicate whether an interrupt is pending. When bit 0 is a logic "0", an interrupt is pending and the contents of the IIR may be used as a pointer to the appropriate internal service routine. When bit 0 is a logic "1", no interrupt is pending. Bits 1 and 2 These two bits of the IIR are used to identify the highest priority interrupt pending as indicated by the Interrupt Control Table. Bit 3 Bit 7 Bit 6 0 0 1 1 0 1 0 1 RCVR FIFO Trigger Level (BYTES) 1 4 8 14 INTERRUPT IDENTIFICATION REGISTER (IIR) Address Offset = 2H, DLAB = X, READ By accessing this register, the host CPU can determine the highest priority interrupt and its source. Four levels of priority interrupt exist. They are in descending order of priority: 1. Receiver Line Status (highest priority) 2. Received Data Ready In non-FIFO mode, this bit is a logic "0". In FIFO mode this bit is set along with bit 2 when a timeout interrupt is pending. Bits 4 and 5 These bits of the IIR are always logic "0". Bits 6 and 7 These two bits are set when the FIFO CONTROL Register bit 0 equals 1. 75 Table 32 - Interrupt Control Table FIFO MODE ONLY BIT 3 0 0 INTERRUPT IDENTIFICATION REGISTER BIT 2 BIT 1 0 1 0 1 BIT 0 1 0 PRIORITY LEVEL Highest INTERRUPT SET AND RESET FUNCTIONS INTERRUPT TYPE None Receiver Line Status INTERRUPT SOURCE None Overrun Error, Parity Error, Framing Error or Break Interrupt INTERRUPT RESET CONTROL Reading the Line Status Register 0 1 0 0 Second Received Data Receiver Data Available Available Read Receiver Buffer or the FIFO drops below the trigger level. Reading the Receiver Buffer Register 1 1 0 0 Second Character Timeout Indication No Characters Have Been Removed From or Input to the RCVR FIFO during the last 4 Char times and there is at least 1 char in it during this time Transmitter Holding Register Empty 0 0 1 0 Third Transmitter Holding Register Empty Reading the IIR Register (if Source of Interrupt) or Writing the Transmitter Holding Register Reading the MODEM Status Register 0 0 0 0 Fourth MODEM Status Clear to Send or Data Set Ready or Ring Indicator or Data Carrier Detect 76 LINE CONTROL REGISTER (LCR) Address Offset = 3H, DLAB = 0, READ/WRITE This register contains the format information of the serial line. The bit definitions are: Bits 0 and 1 These two bits specify the number of bits in each transmitted or received serial character. The encoding of bits 0 and 1 is as follows: BIT 1 0 0 1 1 BIT 0 WORD LENGTH 0 1 0 1 5 Bits 6 Bits 7 Bits 8 Bits checked (receive data) between the last data word bit and the first stop bit of the serial data. (The parity bit is used to generate an even or odd number of 1s when the data word bits and the parity bit are summed). Bit 4 Even Parity Select bit. When bit 3 is a logic "1" and bit 4 is a logic "0", an odd number of logic "1"'s is transmitted or checked in the data word bits and the parity bit. When bit 3 is a logic "1" and bit 4 is a logic "1" an even number of bits is transmitted and checked. Bit 5 Stick Parity bit. When bit 3 is a logic "1" and bit 5 is a logic "1", the parity bit is transmitted and then detected by the receiver in the opposite state indicated by bit 4. Bit 6 Set Break Control bit. When bit 6 is a logic "1", the transmit data output (TXD) is forced to the Spacing or logic "0" state and remains there (until reset by a low level bit 6) regardless of other transmitter activity. This feature enables the Serial Port to alert a terminal in a communications system. Bit 7 Divisor Latch Access bit (DLAB). It must be set high (logic "1") to access the Divisor Latches of the Baud Rate Generator during read or write operations. It must be set low (logic "0") to access the Receiver Buffer Register, the Transmitter Holding Register, or the Interrupt Enable Register. MODEM CONTROL REGISTER (MCR) Address Offset = 4H, DLAB = READ/WRITE The Start, Stop and Parity bits are not included in the word length. Bit 2 This bit specifies the number of stop bits in each transmitted or received serial character. The following table summarizes the information. NUMBER OF STOP BITS 1 1.5 2 2 2 BIT 2 0 1 1 1 1 WORD LENGTH -5 bits 6 bits 7 bits 8 bits Note: The receiver will ignore all stop bits beyond the first, regardless of the number used in transmitting. Bit 3 Parity Enable bit. When bit 3 is a logic "1", a parity bit is generated (transmit data) or X, This 8 bit register controls the interface with the MODEM or data set (or device emulating a MODEM). The contents of the MODEM control register are described below. 77 Bit 0 This bit controls the Data Terminal Ready (nDTR) output. When bit 0 is set to a logic "1", the nDTR output is forced to a logic "0". When bit 0 is a logic "0", the nDTR output is forced to a logic "1". Bit 1 This bit controls the Request To Send (nRTS) output. Bit 1 affects the nRTS output in a manner identical to that described above for bit 0. Bit 2 This bit controls the Output 1 (OUT1) bit. This bit does not have an output pin and can only be read or written by the CPU. Bit 3 Output 2 (OUT2). This bit is used to enable an UART interrupt. When OUT2 is a logic "0", the serial port interrupt output is forced to a high impedance state - disabled. When OUT2 is a logic "1", the serial port interrupt outputs are enabled. Bit 4 This bit provides the loopback feature for diagnostic testing of the Serial Port. When bit 4 is set to logic "1", the following occur: 1. The TXD is set to the Marking State(logic "1"). 2. The receiver Serial Input (RXD) is disconnected. 3. The output of the Transmitter Shift Register is "looped back" into the Receiver Shift Register input. 4. All MODEM Control inputs (nCTS, nDSR, nRI and nDCD) are disconnected. 5. The four MODEM Control outputs (nDTR, nRTS, OUT1 and OUT2) are internally connected to the four MODEM Control inputs (nDSR, nCTS, RI and DCD) respectively. 6. The Modem Control output pins are forced inactive high. 7. Data that is transmitted is immediately received. This feature allows the processor to verify the transmit and receive data paths of the Serial Port. In the diagnostic mode, the receiver and the transmitter interrupts are fully operational. The MODEM Control Interrupts are also operational but the interrupts' sources are now the lower four bits of the MODEM Control Register instead of the MODEM Control inputs. The interrupts are still controlled by the Interrupt Enable Register. Bits 5 through 7 These bits are permanently set to logic zero. LINE STATUS REGISTER (LSR) Address Offset = 5H, DLAB = X, READ/WRITE Bit 0 Data Ready (DR). It is set to a logic "1" whenever a complete incoming character has been received and transferred into the Receiver Buffer Register or the FIFO. Bit 0 is reset to a logic "0" by reading all of the data in the Receive Buffer Register or the FIFO. Bit 1 Overrun Error (OE). Bit 1 indicates that data in the Receiver Buffer Register was not read before the next character was transferred into the register, thereby destroying the previous character. In FIFO mode, an overrunn error will occur only when the FIFO is full and the next character has been completely received in the shift register, the character in the shift register is overwritten but not transferred to the FIFO. The OE indicator is set to a logic "1" immediately upon detection of an overrun condition, and reset whenever the Line Status Register is read. Bit 2 Parity Error (PE). Bit 2 indicates that the received data character does not have the correct even or odd parity, as selected by the even parity select bit. The PE is set to a logic "1" upon detection of a parity error and is reset to a logic "0" whenever the Line Status Register is read. In the FIFO mode this error is associated with the particular character in the FIFO it applies to. This error is indicated when 78 the associated character is at the top of the FIFO. Bit 3 Framing Error (FE). Bit 3 indicates that the received character did not have a valid stop bit. Bit 3 is set to a logic "1" whenever the stop bit following the last data bit or parity bit is detected as a zero bit (Spacing level). The FE is reset to a logic "0" whenever the Line Status Register is read. In the FIFO mode this error is associated with the particular character in the FIFO it applies to. This error is indicated when the associated character is at the top of the FIFO. The Serial Port will try to resynchronize after a framing error. To do this, it assumes that the framing error was due to the next start bit, so it samples this 'start' bit twice and then takes in the 'data'. Bit 4 Break Interrupt (BI). Bit 4 is set to a logic "1" whenever the received data input is held in the Spacing state (logic "0") for longer than a full word transmission time (that is, the total time of the start bit + data bits + parity bits + stop bits). The BI is reset after the CPU reads the contents of the Line Status Register. In the FIFO mode this error is associated with the particular character in the FIFO it applies to. This error is indicated when the associated character is at the top of the FIFO. When break occurs only one zero character is loaded into the FIFO. Restarting after a break is received, requires the serial data (RXD) to be logic "1" for at least 1/2 bit time. Note: Bits 1 through 4 are the error conditions that produce a Receiver Line Status Interrupt whenever any of the corresponding conditions are detected and the interrupt is enabled. Bit 5 Transmitter Holding Register Empty (THRE). Bit 5 indicates that the Serial Port is ready to accept a new character for transmission. In addition, this bit causes the Serial Port to issue an interrupt when the Transmitter Holding Register interrupt enable is set high. The THRE bit is set to a logic "1" when a character is transferred from the Transmitter Holding Register into the Transmitter Shift Register. The bit is reset to logic "0" whenever the CPU loads the Transmitter Holding Register. In the FIFO mode this bit is set when the XMIT FIFO is empty, it is cleared when at least 1 byte is written to the XMIT FIFO. Bit 5 is a read only bit. Bit 6 Transmitter Empty (TEMT). Bit 6 is set to a logic "1" whenever the Transmitter Holding Register (THR) and Transmitter Shift Register (TSR) are both empty. It is reset to logic "0" whenever either the THR or TSR contains a data character. Bit 6 is a read only bit. In the FIFO mode this bit is set whenever the THR and TSR are both empty, Bit 7 This bit is permanently set to logic "0" in the 450 mode. In the FIFO mode, this bit is set to a logic "1" when there is at least one parity error, framing error or break indication in the FIFO. This bit is cleared when the LSR is read if there are no subsequent errors in the FIFO. MODEM STATUS REGISTER (MSR) Address Offset = 6H, DLAB = X, READ/WRITE This 8 bit register provides the current state of the control lines from the MODEM (or peripheral device). In addition to this current state information, four bits of the MODEM Status Register (MSR) provide change information. These bits are set to logic "1" whenever a control input from the MODEM changes state. They are reset to logic "0" whenever the MODEM Status Register is read. 79 Bit 0 Delta Clear To Send (DCTS). Bit 0 indicates that the nCTS input to the chip has changed state since the last time the MSR was read. Bit 1 Delta Data Set Ready (DDSR). Bit 1 indicates that the nDSR input has changed state since the last time the MSR was read. Bit 2 Trailing Edge of Ring Indicator (TERI). Bit 2 indicates that the nRI input has changed from logic "0" to logic "1". Bit 3 Delta Data Carrier Detect (DDCD). Bit 3 indicates that the nDCD input to the chip has changed state. NOTE: Whenever bit 0, 1, 2, or 3 is set to a logic "1", a MODEM Status Interrupt is generated. Bit 4 This bit is the complement of the Clear To Send (nCTS) input. If bit 4 of the MCR is set to logic "1", this bit is equivalent to nRTS in the MCR. Bit 5 This bit is the complement of the Data Set Ready (nDSR) input. If bit 4 of the MCR is set to logic "1", this bit is equivalent to DTR in the MCR. Bit 6 This bit is the complement of the Ring Indicator (nRI) input. If bit 4 of the MCR is set to logic "1", this bit is equivalent to OUT1 in the MCR. Bit 7 This bit is the complement of the Data Carrier Detect (nDCD) input. If bit 4 of the MCR is set to logic "1", this bit is equivalent to OUT2 in the MCR. SCRATCHPAD REGISTER (SCR) Address Offset =7H, DLAB =X, READ/WRITE This 8 bit read/write register has no effect on the operation of the Serial Port. It is intended as a scratchpad register to be used by the programmer to hold data temporarily. PROGRAMMABLE BAUD RATE GENERATOR (AND DIVISOR LATCHES DLH, DLL) The Serial Port contains a programmable Baud Rate Generator that is capable of taking any clock input (DC to 3 MHz) and dividing it by any divisor from 1 to 65535. This output frequency of the Baud Rate Generator is 16x the Baud rate. Two 8 bit latches store the divisor in 16 bit binary format. These Divisor Latches must be loaded during initialization in order to insure desired operation of the Baud Rate Generator. Upon loading either of the Divisor Latches, a 16 bit Baud counter is immediately loaded. This prevents long counts on initial load. If a 0 is loaded into the BRG registers the output divides the clock by the number 3. If a 1 is loaded the output is the inverse of the input oscillator. If a two is loaded the output is a divide by 2 signal with a 50% duty cycle. If a 3 or greater is loaded the output is low for 2 bits and high for the remainder of the count. The input clock to the BRG is the 24 MHz crystal divided by 13, giving a 1.8462 MHz clock. Table 33 shows the baud rates possible with a 1.8462 MHz crystal. Effect Of The Reset on Register File The Reset Function Table (Table 34) details the effect of the Reset input on each of the registers of the Serial Port. 80 FIFO INTERRUPT MODE OPERATION When the RCVR FIFO and receiver interrupts are enabled (FCR bit 0 = "1", IER bit 0 = "1"), RCVR interrupts occur as follows: A. The receive data available interrupt will issued when the FIFO has reached programmed trigger level; it is cleared soon as the FIFO drops below programmed trigger level. be its as its B. Character times are calculated by using the RCLK input for a clock signal (this makes the delay proportional to the baudrate). C. When a timeout interrupt has occurred it is cleared and the timer reset when the CPU reads one character from the RCVR FIFO. D. When a timeout interrupt has not occurred the timeout timer is reset after a new character is received or after the CPU reads the RCVR FIFO. When the XMIT FIFO and transmitter interrupts are enabled (FCR bit 0 = "1", IER bit 1 = "1"), XMIT interrupts occur as follows: A. The transmitter holding register interrupt (02H) occurs when the XMIT FIFO is empty; it is cleared as soon as the transmitter holding register is written to (1 of 16 characters may be written to the XMIT FIFO while servicing this interrupt) or the IIR is read. B. The transmitter FIFO empty indications will be delayed 1 character time minus the last stop bit time whenever the following occurs: THRE=1 and there have not been at least two bytes at the same time in the transmitter FIFO since the last THRE=1. The transmitter interrupt after changing FCR0 will be immediate, if it is enabled. Character timeout and RCVR FIFO trigger level interrupts have the sme priority as the current received data available interrupt; XMIT FIFO empty has the same priority as the current transmitter holding register empty interrupt. FIFO POLLED MODE OPERATION With FCR bit 0 = "1" resetting IER bits 0, 1, 2 or 3 or all to zero puts the UART in the FIFO Polled Mode of operation. Since the RCVR and B. The IIR receive data available indication also occurs when the FIFO trigger level is reached. It is cleared when the FIFO drops below the trigger level. C. The receiver line status interrupt (IIR=06H), has higher priority than the received data available (IIR=04H) interrupt. D. The data ready bit (LSR bit 0)is set as soon as a character is transferred from the shift register to the RCVR FIFO. It is reset when the FIFO is empty. When RCVR FIFO and receiver interrupts are enabled, RCVR FIFO timeout interrupts occur as follows: A. A FIFO timeout interrupt occurs if all the following conditions exist: - At least one character is in the FIFO - The most recent serial character received was longer than 4 continuous character times ago. (If 2 stop bits are programmed, the second one is included in this time delay.) - The most recent CPU read of the FIFO was longer than 4 continuous character times ago. This will cause a maximum character received to interrupt issued delay of 160 msec at 300 BAUD with a 12 bit character. 81 XMITTER are controlled separately, either one or both can be in the polled mode of operation. In this mode, the user's program will check RCVR and XMITTER status via the LSR. LSR definitions for the FIFO Polled Mode are as follows: Bit 0=1 as long as there is one byte in the RCVR FIFO. Bits 1 to 4 specify which error(s) have occurred. Character error status is handled the same way as when in the interrupt - mode, the IIR is not affected since EIR bit 2=0. Bit 5 indicates when the XMIT FIFO is empty. Bit 6 indicates that both the XMIT FIFO and shift register are empty. Bit 7 indicates whether there are any errors in the RCVR FIFO. There is no trigger level reached or timeout condition indicated in the FIFO Polled Mode, however, the RCVR and XMIT FIFOs are still fully capable of holding characters. DESIRED BAUD RATE 50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 57600 115200 230400 460800 Table 33 - Baud Rates Using 1.8462 MHz Clock (24 MHz/13) DIVISOR USED TO PERCENT ERROR DIFFERENCE GENERATE 16X CLOCK BETWEEN DESIRED AND ACTUAL* 2307 1538 1049 858 769 384 192 96 64 58 48 32 24 16 12 6 3 2 1 32770 32769 0.03 0.03 0.005 0.01 0.03 0.16 0.16 0.16 0.16 0.5 0.16 0.16 0.16 0.16 0.16 0.16 0.16 1.6 0.16 0.16 0.16 CROC: BIT 7 OR 6 X X X X X X X X X X X X X X X X X X X 1 1 82 REGISTER/SIGNAL Interrupt Enable Register Interrupt Identification Reg. FIFO Control Line Control Reg. MODEM Control Reg. Line Status Reg. MODEM Status Reg. TXD1, TXD2 INTRPT (RCVR errs) INTRPT (RCVR Data Ready) INTRPT (THRE) OUT2B RTSB DTRB OUT1B RCVR FIFO XMIT FIFO Table 34 - Reset Function Table RESET CONTROL RESET RESET RESET RESET RESET RESET RESET RESET RESET/Read LSR RESET/Read RBR RESET/ReadIIR/Write THR RESET RESET RESET RESET RESET/FCR1*FCR0/ FCR0 RESET/FCR1*FCR0/ FCR0 RESET STATE All bits low Bit 0 is high; Bits 1 thru 7 low All bits low All bits low All bits low All bits low except 5, 6 high Bits 0 - 3 low; Bits 4 - 7 input High Low Low Low High High High High All Bits Low All Bits Low 83 Table 35 - Register Summary for an Individual UART Channel REGISTER ADDRESS* ADDR = 0 DLAB = 0 ADDR = 0 DLAB = 0 ADDR = 1 DLAB = 0 REGISTER NAME Receive Buffer Register (Read Only) Transmitter Holding Register (Write Only) Interrupt Enable Register REGISTER SYMBOL RBR THR IER BIT 0 Data Bit 0 (Note 1) Data Bit 0 Enable Received Data Available Interrupt (ERDAI) BIT 1 Data Bit 1 Data Bit 1 Enable Transmitter Holding Register Empty Interrupt (ETHREI) ADDR = 2 ADDR = 2 ADDR = 3 Interrupt Ident. Register (Read Only) FIFO Control Register (Write Only) Line Control Register IIR FCR LCR "0" if Interrupt Interrupt ID Pending Bit FIFO Enable Word Length Select Bit 0 (WLS0) Data Terminal Ready (DTR) Data Ready (DR) RCVR FIFO Reset Word Length Select Bit 1 (WLS1) Request to Send (RTS) Overrun Error (OE) ADDR = 4 MODEM Control Register MCR ADDR = 5 ADDR = 6 Line Status Register MODEM Status Register LSR MSR Delta Clear to Delta Data Send (DCTS) Set Ready (DDSR) Bit 0 Bit 0 Bit 8 Bit 1 Bit 1 Bit 9 ADDR = 7 ADDR = 0 DLAB = 1 ADDR = 1 DLAB = 1 Scratch Register (Note 4) Divisor Latch (LS) Divisor Latch (MS) SCR DDL DLM *DLAB is Bit 7 of the Line Control Register (ADDR = 3). Note 1: Bit 0 is the least significant bit. It is the first bit serially transmitted or received. Note 2: When operating in the XT mode, this bit will be set any time that the transmitter shift register is empty. 84 Table 35 - Register Summary for an Individual UART Channel (continued) BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 Data Bit 2 Data Bit 2 Enable Receiver Line Status Interrupt (ELSI) Interrupt ID Bit XMIT FIFO Reset Number of Stop Bits (STB) OUT1 (Note 3) Parity Error (PE) Data Bit 3 Data Bit 3 Enable MODEM Status Interrupt (EMSI) Interrupt ID Bit (Note 5) DMA Mode Select (Note 6) Parity Enable (PEN) OUT2 (Note 3) Data Bit 4 Data Bit 4 0 Data Bit 5 Data Bit 5 0 Data Bit 6 Data Bit 6 0 Data Bit 7 Data Bit 7 0 0 0 FIFOs Enabled (Note 5) FIFOs Enabled (Note 5) Reserved Reserved RCVR Trigger RCVR Trigger LSB MSB Set Break Divisor Latch Access Bit (DLAB) 0 Error in RCVR FIFO (Note 5) Even Parity Select (EPS) Loop Stick Parity 0 Transmitter Holding Register (THRE) Data Set Ready (DSR) Bit 5 Bit 5 Bit 13 0 Transmitter Empty (TEMT) (Note 2) Framing Error Break (FE) Interrupt (BI) Trailing Edge Delta Data Clear to Send Ring Indicator Carrier Detect (CTS) (TERI) (DDCD) Bit 2 Bit 2 Bit 10 Note 3: Note 4: Note 5: Note 6: Bit 3 Bit 3 Bit 11 Bit 4 Bit 4 Bit 12 Ring Indicator Data Carrier Detect (DCD) (RI) Bit 6 Bit 6 Bit 14 Bit 7 Bit 7 Bit 15 This bit no longer has a pin associated with it. When operating in the XT mode, this register is not available. These bits are always zero in the non-FIFO mode. Writing a one to this bit has no effect. DMA modes are not supported in this chip. 85 NOTES ON SERIAL PORT OPERATION FIFO MODE OPERATION: GENERAL The RCVR FIFO will hold up to 16 bytes regardless of which trigger level is selected. TX AND RX FIFO OPERATION The Tx portion of the UART transmits data through TXD as soon as the CPU loads a byte into the Tx FIFO. The UART will prevent loads to the Tx FIFO if it currently holds 16 characters. Loading to the Tx FIFO will again be enabled as soon as the next character is transferred to the Tx shift register. These capabilities account for the largely autonomous operation of the Tx. The UART starts the above operations typically with a Tx interrupt. The chip issues a Tx interrupt whenever the Tx FIFO is empty and the Tx interrupt is enabled, except in the following instance. Assume that the Tx FIFO is empty and the CPU starts to load it. When the first byte enters the FIFO the Tx FIFO empty interrupt will transition from active to inactive. Depending on the execution speed of the service routine software, the UART may be able to transfer this byte from the FIFO to the shift register before the CPU loads another byte. If this happens, the Tx FIFO will be empty again and typically the UART's interrupt line would transition to the active state. This could cause a system with an interrupt control unit to record a Tx FIFO empty condition, even though the CPU is currently servicing that interrupt. Therefore, after the first byte has been loaded into the FIFO the UART will wait one serial character transmission time before issuing a new Tx FIFO empty interrupt. This one character Tx interrupt delay will remain active until at least two bytes have been loaded into the FIFO, concurrently. When the Tx FIFO empties after this condition, the Tx interrupt will be activated without a one character delay. Rx support functions and operation are quite different from those described for the transmitter. The Rx FIFO receives data until the number of bytes in the FIFO equals the selected interrupt trigger level. At that time if Rx interrupts are enabled, the UART will issue an interrupt to the CPU. The Rx FIFO will continue to store bytes until it holds 16 of them. It will not accept any more data when it is full. Any more data entering the Rx shift register will set the Overrun Error flag. Normally, the FIFO depth and the programmable trigger levels will give the CPU ample time to empty the Rx FIFO before an overrun occurs. One side-effect of having a Rx FIFO is that the selected interrupt trigger level may be above the data level in the FIFO. This could occur when data at the end of the block contains fewer bytes than the trigger level. No interrupt would be issued to the CPU and the data would remain in the UART. To prevent the software from having to check for this situation the chip incorporates a timeout interrupt. The timeout interrupt is activated when there is a least one byte in the Rx FIFO, and neither the CPU nor the Rx shift register has accessed the Rx FIFO within 4 character times of the last byte. The timeout interrupt is cleared or reset when the CPU reads the Rx FIFO or another character enters it. These FIFO related features allow optimization of CPU/UART transactions and are especially useful given the higher baud rate capability (256 kbaud). 86 INFRARED INTERFACE The FDC37C669's infrared interface provides a two-way wireless communications port using infrared as a transmission medium. Two infrared implementations have been provided in the FDC37C669, IrDA and Amplitude Shift Keyed IR. IrDA allows serial communication at baud rates up to 115K Baud. Each word is sent serially beginning with a zero value start bit. A zero is signaled by sending a single infrared pulse at the beginning of the serial bit time. A one is signaled by sending no infrared pulse during the bit time. Please refer to the AC timing for the parameters of these pulses and the IrDA waveform. The Amplitude Shift Keyed infrared allows serial communication at baud rates up to 19.2K Baud. Each word is sent serially beginning with a zero value start bit. A zero is signaled by sending a 500kHz waveform for the duration of the serial bit time. A one is signaled by sending no transmission the bit time. Please refer to the AC timing for the parameters of the ASKIR waveform. If the Half Duplex option is chosen, there is a time-out when the direction of the transmission is changed. This time-out starts at the last bit transferred during a transmission and blocks the receiver input until the time-out expires. If the transmit buffer is loaded with more data before the time-out expires, the timer is restarted after the new byte is transmitted. If data is loaded into the transmit buffer while a character is being received, the transmission will not start until the time-out expires after the last receive bit has been received. If the start bit of another character is received during this time-out, the timer is restarted after the new character is received. The time-out is four character times. A character time is defined as 10 bit times regardless of the actual word length being used. 87 PARALLEL PORT The FDC37C669 incorporates an IBM XT/AT compatible parallel port. The FDC37C669 supports the optional PS/2 type bi-directional parallel port (SPP), the Enhanced Parallel Port (EPP) and the Extended Capabilities Port (ECP) parallel port modes. Refer to the FDC37C669 Configuration Registers and FDC37C669 Hardware Configuration description for information on disabling, power down, changing the base address of the parallel port, and selecting the mode of operation. DATA PORT BASE ADDRESS + 00H STATUS PORT BASE ADDRESS + 01H CONTROL PORT BASE ADDRESS + 02H EPP ADDR PORT BASE ADDRESS + 03H The bit map of these registers is: D0 PD0 TMOUT D1 PD1 0 D2 PD2 0 nINIT PD2 PD2 PD2 PD2 PD2 D3 PD3 nERR SLC PD3 PD3 PD3 PD3 PD3 The FDC37C669 also incorporates SMSC's ChiProtect circuitry, which prevents possible damage to the parallel port due to printer powerup. The functionality of the Parallel Port is achieved through the use of eight addressable ports, with their associated registers and control gating. The control and data port are read/write by the CPU, the status port is read/write in the EPP mode. The address map of the Parallel Port is shown below: EPP DATA PORT 0 BASE ADDRESS + 04H EPP DATA PORT 1 BASE ADDRESS + 05H EPP DATA PORT 2 BASE ADDRESS + 06H EPP DATA PORT 3 BASE ADDRESS + 07H DATA PORT STATUS PORT CONTROL PORT EPP ADDR PORT EPP DATA PORT 0 EPP DATA PORT 1 EPP DATA PORT 2 EPP DATA PORT 3 D4 PD4 SLCT IRQE PD4 PD4 PD4 PD4 PD4 D5 PD5 PE PCD PD5 PD5 PD5 PD5 PD5 D6 PD6 nACK 0 PD6 PD6 PD6 PD6 PD6 D7 PD7 nBUSY 0 AD7 PD7 PD7 PD7 PD7 Note 1 1 1 2,3 2,3 2,3 2,3 2,3 STROBE AUTOFD PD0 PD0 PD0 PD0 PD0 PD1 PD1 PD1 PD1 PD1 Note 1: These registers are available in all modes. Note 2: These registers are only available in EPP mode. Note 3: For EPP mode, IOCHRDY must be connected to the ISA bus. 88 Table 36 - Parallel Port Connector HOST CONNECTOR 1 2-9 10 11 12 13 14 15 16 17 (1) = Compatible Mode (3) = High Speed Mode Note: For the cable interconnection required for ECP support and the Slave Connector pin numbers, refer to the IEEE 1284 Extended Capabilities Port Protocol and ISA Standard, Rev. 1.09, Jan. 7, 1993. This document is available from Microsoft. PIN NUMBER 77 71-68, 66-63 62 61 60 59 76 75 74 73 STANDARD nStrobe PData<0:7> nAck Busy PE Select nAutofd nError nInit nSelectin nWrite PData<0:7> Intr nWait (NU) (NU) nDatastb (NU) (NU) nAddrstrb EPP nStrobe PData<0:7> nAck Busy, PeriphAck(3) PError, nAckReverse(3) Select nAutoFd, HostAck(3) nFault(1) nPeriphRequest(3) nInit(1) nReverseRqst(3) nSelectIn(1,3) ECP 89 IBM XT/AT COMPATIBLE, BI-DIRECTIONAL AND EPP MODES DATA PORT ADDRESS OFFSET = 00H The Data Port is located at an offset of '00H' from the base address. The data register is cleared at initialization by RESET. During a WRITE operation, the Data Register latches the contents of the data bus with the rising edge of the nIOW input. The contents of this register are buffered (non inverting) and output onto the PD0 - PD7 ports. During a READ operation in SPP mode, PD0 - PD7 ports are buffered (not latched) and output to the host CPU. STATUS PORT ADDRESS OFFSET = 01H The Status Port is located at an offset of '01H' from the base address. The contents of this register are latched for the duration of an nIOR read cycle. The bits of the Status Port are defined as follows: BIT 0 TMOUT - TIME OUT This bit is valid in EPP mode only and indicates that a 10 usec time out has occured on the EPP bus. A logic O means that no time out error has occured; a logic 1 means that a time out error has been detected. This bit is cleared by a RESET. Writing a one to this bit clears the time out status bit. On a write, this bit is self clearing and does not require a write of a zero. Writing a zero to this bit has no effect. BITS 1, 2 - are not implemented as register bits, during a read of the Printer Status Register these bits are a low level. BIT 3 nERR - nERROR The level on the nERROR input is read by the CPU as bit 3 of the Printer Status Register. A logic O means an error has been detected; a logic 1 means no error has been detected. BIT 4 SLCT - PRINTER SELECTED STATUS The level on the SLCT input is read by the CPU as bit 4 of the Printer Status Register. A logic 1 means the printer is on line; a logic 0 means it is not selected. BIT 5 PE - PAPER END The level on the PE input is read by the CPU as bit 5 of the Printer Status Register. A logic 1 indicates a paper end; a logic 0 indicates the presence of paper. BIT 6 nACK - nACKNOWLEDGE The level on the nACK input is read by the CPU as bit 6 of the Printer Status Register. A logic 0 means that the printer has received a character and can now accept another. A logic 1 means that it is still processing the last character or has not received the data. BIT 7 nBUSY - nBUSY The complement of the level on the nBUSY input is read by the CPU as bit 7 of the Printer Status Register. A logic 0 in this bit means that the printer is busy and cannot accept a new character. A logic 1 means that it is ready to accept the next character. CONTROL PORT ADDRESS OFFSET = 02H The Control Port is located at an offset of '02H' from the base address. The Control Register is initialized by the RESET input, bits 0 to 5 only being affected; bits 6 and 7 are hard wired low. 90 BIT 0 STROBE - STROBE This bit is inverted and output onto the nSTROBE output. BIT 1 AUTOFD - AUTOFEED This bit is inverted and output onto the nAUTOFD output. A logic 1 causes the printer to generate a line feed after each line is printed. A logic 0 means no autofeed. BIT 2 nINIT - nINITIATE OUTPUT This bit is output onto the nINIT output without inversion. BIT 3 SLCTIN - PRINTER SELECT INPUT This bit is inverted and output onto the nSLCTIN output. A logic 1 on this bit selects the printer; a logic 0 means the printer is not selected. BIT 4 IRQE - INTERRUPT REQUEST ENABLE The interrupt request enable bit when set to a high level may be used to enable interrupt requests from the Parallel Port to the CPU. An interrupt request is generated on the IRQ port by a positive going nACK input. When the IRQE bit is programmed low the IRQ is disabled. BIT 5 PCD - PARALLEL CONTROL DIRECTION the PD0 - PD7 ports, the leading edge of nIOW causes an EPP ADDRESS WRITE cycle to be performed, the trailing edge of IOW latches the data for the duration of the EPP write cycle. During a READ operation, PD0 - PD7 ports are read, the leading edge of IOR causes an EPP ADDRESS READ cycle to be performed and the data output to the host CPU, the deassertion of ADDRSTB latches the PData for the duration of the IOR cycle. This register is only available in EPP mode. EPP DATA PORT 0 ADDRESS OFFSET = 04H The EPP Data Port 0 is located at an offset of '04H' from the base address. The data register is cleared at initialization by RESET. During a WRITE operation, the contents of DB0-DB7 are buffered (non inverting) and output onto the PD0 - PD7 ports, the leading edge of nIOW causes an EPP DATA WRITE cycle to be performed, the trailing edge of IOW latches the data for the duration of the EPP write cycle. During a READ operation, PD0 - PD7 ports are read, the leading edge of IOR causes an EPP READ cycle to be performed and the data output to the host CPU, the deassertion of DATASTB latches the PData for the duration of the IOR cycle. This register is only available in EPP mode. EPP DATA PORT 1/ADDRESS OFFSET = 05H The EPP Data Port 1 is located at an offset of '05H' from the base address. Refer to EPP DATA PORT 0 for a description of operation. This register is only available in EPP mode. EPP DATA PORT 2/ADDRESS OFFSET = 06H Parallel Control Direction is valid in extended mode only (CR#1<3>=0). In printer mode, the direction is always out regardless of the state of this bit. In bi-directional mode, a logic 0 means that the printer port is in output mode (write); a logic 1 means that the printer port is in input mode (read). Bits 6 and 7 during a read are a low level, and cannot be written. EPP ADDRESS PORT ADDRESS OFFSET = 03H The EPP Address Port is located at an offset of '03H' from the base address. The address register is cleared at initialization by RESET. During a WRITE operation, the contents of DB0DB7 are buffered (non inverting) and output onto The EPP Data Port 2 is located at an offset of '06H' from the base address. Refer to EPP DATA PORT 0 for a description of operation. This register is only available in EPP mode. EPP DATA PORT 3 ADDRESS OFFSET = 07H 91 The EPP Data Port 3 is located at an offset of '07H' from the base address. Refer to EPP DATA PORT 0 for a description of operation. This register is only available in EPP mode. EPP 1.9 OPERATION When the EPP mode is selected in the configuration register, the standard and bidirectional modes are also available. If no EPP Read, Write or Address cycle is currently executing, then the PDx bus is in the standard or bi-directional mode, and all output signals (STROBE, AUTOFD, INIT) are as set by the SPP Control Port and direction is controlled by PCD of the Control port. In EPP mode, the system timing is closely coupled to the EPP timing. For this reason, a watchdog timer is required to prevent system lockup. The timer indicates if more than 10usec have elapsed from the start of the EPP cycle (nIOR or nIOW asserted) to nWAIT being deasserted (after command). If a time-out occurs, the current EPP cycle is aborted and the time-out condition is indicated in Status bit 0. During an EPP cycle, if STROBE is active, it overrides the EPP write signal forcing the PDx bus to always be in a write mode and the nWRITE signal to always be asserted. Software Constraints Before an EPP cycle is executed, the software must ensure that the control register bit PCD is a logic "0" (i.e. a 04H or 05H should be written to the Control port). If the user leaves PCD as a logic "1", and attempts to perform an EPP write, the chip is unable to perform the write (because PCD is a logic "1") and will appear to perform an EPP read on the parallel bus, no error is indicated. EPP 1.9 Write The timing for a write operation (address or data) is shown in timing diagram EPP 1.9 Write Data or Address cycle. IOCHRDY is driven active low at the start of each EPP write and is released when it has been determined that the write cycle can complete. The write cycle can complete under the following circumstances: 1. If the EPP bus is not ready (nWAIT is active low) when nDATASTB or nADDRSTB goes active then the write can complete when nWAIT goes inactive high. If the EPP bus is ready (nWAIT is inactive high) then the chip must wait for it to go active low before changing the state of nDATASTB, nWRITE or nADDRSTB. The write can complete once nWAIT is determined inactive. 2. Write Sequence of operation 1. The host selects an EPP register, places data on the SData bus and drives nIOW active. The chip drives IOCHRDY inactive (low). If WAIT is not asserted, the chip must wait until WAIT is asserted. The chip places address or data on PData bus, clears PDIR, and asserts nWRITE. Chip asserts nDATASTB or nADDRSTRB indicating that PData bus contains valid information, and the WRITE signal is valid. Peripheral deasserts nWAIT, indicating that any setup requirements have been satisfied and the chip may begin the termination phase of the cycle. a) The chip deasserts nDATASTB or nADDRSTRB, this marks the beginning of the termination phase. If it has not already done so, the peripheral should latch the information byte now. b) The chip latches the data from the SData bus for the PData bus and asserts (releases) IOCHRDY allowing the host to complete the write cycle. 2. 3. 4. 5. 6. 7. 92 8. 9. Peripheral asserts nWAIT, indicating to the host that any hold time requirements have been satisfied and acknowledging the termination of the cycle. Chip may modify nWRITE and nPDATA in preparation for the next cycle. EPP 1.9 Read The timing for a read operation (data) is shown in timing diagram EPP Read Data cycle. IOCHRDY is driven active low at the start of each EPP read and is released when it has been determined that the read cycle can complete. The read cycle can complete under the following circumstances: 1. If the EPP bus is not ready (nWAIT is active low) when nDATASTB goes active then the read can complete when nWAIT goes inactive high. If the EPP bus is ready (nWAIT is inactive high) then the chip must wait for it to go active low before changing the state of WRITE or before nDATASTB goes active. The read can complete once nWAIT is determined inactive. deasserts nDATASTB or nADDRSTRB, this marks the beginning of the termination phase. b) The chip drives the valid data onto the SData bus and asserts (releases) IOCHRDY allowing the host to complete the read cycle. 9. Peripheral tri-states the PData bus and asserts nWAIT, indicating to the host that the PData bus is tri-stated. 10. Chip may modify nWRITE, PDIR and nPDATA in preparation for the next cycle. EPP 1.7 OPERATION When the EPP 1.7 mode is selected in the configuration register, the standard and bidirectional modes are also available. If no EPP Read, Write or Address cycle is currently executing, then the PDx bus is in the standard or bi-directional mode, and all output signals (STROBE, AUTOFD, INIT) are as set by the SPP Control Port and direction is controlled by PCD of the Control port. In EPP mode, the system timing is closely coupled to the EPP timing. For this reason, a watchdog timer is required to prevent system lockup. The timer indicates if more than 10usec have elapsed from the start of the EPP cycle (nIOR or nIOW asserted) to the end of the cycle nIOR or nIOW deasserted). If a time-out occurs, the current EPP cycle is aborted and the time-out condition is indicated in Status bit 0. Software Constraints Before an EPP cycle is executed, the software must ensure that the control register bits D0, D1 and D3 are set to zero. Also, bit D5 (PCD) is a logic "0" for an EPP write or a logic "1" for and EPP read. EPP 1.7 Write The timing for a write operation (address or data) is shown in timing diagram EPP 1.7 Write 2. Read Sequence of Operation 1. 2. 3. 4. 5. The host selects an EPP register and drives nIOR active. The chip drives IOCHRDY inactive (low). If WAIT is not asserted, the chip must wait until WAIT is asserted. The chip tri-states the PData bus and deasserts nWRITE. Chip asserts nDATASTB or nADDRSTRB indicating that PData bus is tri-stated, PDIR is set and the nWRITE signal is valid. Peripheral drives PData bus valid. Peripheral deasserts nWAIT, indicating that PData is valid and the chip may begin the termination phase of the cycle. a) The chip latches the data from the PData bus for the SData bus, 6. 7. 8. 93 Data or Address cycle. IOCHRDY is driven active low when nWAIT is active low during the EPP cycle. This can be used to extend the cycle time. The write cycle can complete when nWAIT is inactive high. Write Sequence of Operation 1. The host sets PDIR bit in the control register to a logic "0". This asserts nWRITE. The host selects an EPP register, places data on the SData bus and drives nIOW active. The chip places address or data on PData bus. Chip asserts nDATASTB or nADDRSTRB indicating that PData bus contains valid information, and the WRITE signal is valid. If nWAIT is asserted, IOCHRDY is deasserted until the peripheral deasserts nWAIT or a time-out occurs. When the host deasserts nI0W the chip deasserts nDATASTB or nADDRSTRB and latches the data from the SData bus for the PData bus. Chip may modify nWRITE, PDIR and nPDATA in preparation of the next cycle. EPP 1.7 Read The timing for a read operation (data) is shown in timing diagram EPP 1.7 Read Data cycle. IOCHRDY is driven active low when nWAIT is active low during the EPP cycle. This can be used to extend the cycle time. The read cycle can complete when nWAIT is inactive high. Read Sequence of Operation 1. The host sets PDIR bit in the control register to a logic "1". This deasserts nWRITE and tri-states the PData bus. The host selects an EPP register and drives nIOR active. Chip asserts nDATASTB or nADDRSTRB indicating that PData bus is tri-stated, PDIR is set and the nWRITE signal is valid. If nWAIT is asserted, IOCHRDY is deasserted until the peripheral deasserts nWAIT or a time-out occurs. The Peripheral drives PData bus valid. The Peripheral deasserts nWAIT, indicating that PData is valid and the chip may begin the termination phase of the cycle. When the host deasserts nI0R the chip deasserts nDATASTB or nADDRSTRB. Peripheral tri-states the PData bus. Chip may modify nWRITE, PDIR and nPDATA in preparation of the next cycle. 2. 3. 4. 2. 3. 5. 4. 6. 5. 6. 7. 7. 8. 9. 94 Table 37 - EPP Pin Descriptions EPP SIGNAL nWRITE PD<0:7> INTR WAIT EPP NAME nWrite Address/Data Interrupt nWait TYPE O I/O I I EPP DESCRIPTION This signal is active low. It denotes a write operation. Bi-directional EPP byte wide address and data bus. This signal is active high and positive edge triggered. (Pass through with no inversion, Same as SPP). This signal is active low. It is driven inactive as a positive acknowledgement from the device that the transfer of data is completed. It is driven active as an indication that the device is ready for the next transfer. This signal is active low. write operation. It is used to denote data read or DATASTB RESET ADDRSTB PE SLCT nData Strobe nReset nAddress Strobe Paper End Printer Selected Status Error Parallel Port Direction O O O I I This signal is active low. When driven active, the EPP device is reset to its initial operational mode. This signal is active low. or write operation. Same as SPP mode. Same as SPP mode. It is used to denote address read nERR PDIR I O Same as SPP mode. This output shows the direction of the data transfer on the parallel port bus. A low means an output/write condition and a high means an input/read condition. This signal is normally a low (output/write) unless PCD of the control register is set or if an EPP read cycle is in progress. Note 1: SPP and EPP can use 1 common register. Note 2: nWrite is the only EPP output that can be over-ridden by SPP control port during an EPP cycle. For correct EPP read cycles, PCD is required to be a low. 95 EXTENDED CAPABILITIES PARALLEL PORT ECP provides a number of advantages, some of which are listed below. The individual features are explained in greater detail in the remainder of this section. High performance half-duplex forward and * reverse channel Interlocked handshake, for fast reliable * transfer Optional single byte RLE compression for * improved throughput (64:1) Channel addressing for low-cost peripherals * Maintains link and data layer separation * Permits the use of active output drivers * Permits the use of adaptive signal timing * Peer-to-peer capability * Vocabulary The following terms are used in this document: When a signal asserts it transitions to a "true" state, when a signal deasserts it transitions to a "false" state. forward Host to Peripheral communication. reverse Peripheral to Host communication. D7 D6 D5 D4 assert data PD7 PD6 PD5 PD4 ecpAFifo Addr/RL E dsr dcr cFifo ecpDFifo tFifo cnfgA cnfgB ecr 0 compress PWord A port word; equal in size to the width of the ISA interface. For this implementation, PWord is always 8 bits. A high level. 1 A low level. 0 These terms may be considered synonymous: PeriphClk, nAck * HostAck, nAutoFd * PeriphAck, Busy * nPeriphRequest, nFault * nReverseRequest, nInit * nAckReverse, PError * Xflag, Select * ECPMode, nSelectln * HostClk, nStrobe * Reference Document: IEEE 1284 Extended Capabilities Port Protocol and ISA Interface Standard, Rev 1.09, Jan 7, 1993. This document is available from Microsoft. The bit map of the Extended Parallel Port registers is: D3 D2 D1 D0 Note PD3 PD2 PD1 PD0 2 0 nInit 0 0 1 1 2 2 2 0 0 dmaEn 0 0 serviceIntr Address or RLE field nAck 0 PError Direction nBusy 0 Select nFault ackIntEn SelectIn ECP Data FIFO Test FIFO autofd strobe Parallel Port Data FIFO 0 intrValue 0 0 1 0 nErrIntrEn 0 0 full 0 0 empty MODE Note 1: These registers are available in all modes. Note 2: All FIFOs use one common 16 byte FIFO. 96 ISA IMPLEMENTATION STANDARD This specification describes the standard ISA interface to the Extended Capabilities Port (ECP). All ISA devices supporting ECP must meet the requirements contained in this section or the port will not be supported by Microsoft. For a description of the ECP Protocol, please refer to the IEEE 1284 Extended Capabilities Port Protocol and ISA Interface Standard, Rev. 1.09, Jan.7, 1993. This document is available from Microsoft. Description The port is software and hardware compatible with existing parallel ports so that it may be used as a standard LPT port if ECP is not required. The port is designed to be simple and requires a small number of gates to implement. It does not do any "protocol" negotiation, rather it provides an automatic high burst-bandwidth channel that supports DMA for ECP in both the forward and reverse directions. Small FIFOs are employed in both forward and reverse directions to smooth data flow and improve the maximum bandwidth requirement. The size of the FIFO is 16 bytes deep. The port supports an automatic handshake for the standard parallel port to improve compatibility mode transfer speed. The port also supports run length encoded (RLE) decompression (required) in hardware. Compression is accomplished by counting identical bytes and transmitting an RLE byte that indicates how many times the next byte is to be repeated. Decompression simply intercepts the RLE byte and repeats the following byte the specified number of times. Hardware support for compression is optional. 97 NAME nStrobe PData 7:0 nAck PeriphAck (Busy) TYPE O I/O I I Table 38 - ECP Pin Descriptions DESCRIPTION During write operations nStrobe registers data or address into the slave on the asserting edge (handshakes with Busy). Contains address or data or RLE data. Indicates valid data driven by the peripheral when asserted. This signal handshakes with nAutoFd in reverse. This signal deasserts to indicate that the peripheral can accept data. This signal handshakes with nStrobe in the forward direction. In the reverse direction this signal indicates whether the data lines contain ECP command information or data. The peripheral uses this signal to flow control in the forward direction. It is an "interlocked" handshake with nStrobe. PeriphAck also provides command information in the reverse direction. Used to acknowledge a change in the direction the transfer (asserted = forward). The peripheral drives this signal low to acknowledge nReverseRequest. It is an "interlocked" handshake with nReverseRequest. The host relies upon nAckReverse to determine when it is permitted to drive the data bus. Indicates printer on line. Requests a byte of data from the peripheral when asserted, handshaking with nAck in the reverse direction. In the forward direction this signal indicates whether the data lines contain ECP address or data. The host drives this signal to flow control in the reverse direction. It is an "interlocked" handshake with nAck. HostAck also provides command information in the forward phase. Generates an error interrupt when asserted. This signal provides a mechanism for peer-to-peer communication. This signal is valid only in the forward direction. During ECP Mode the peripheral is permitted (but not required) to drive this pin low to request a reverse transfer. The request is merely a "hint" to the host; the host has ultimate control over the transfer direction. This signal would be typically used to generate an interrupt to the host CPU. Sets the transfer direction (asserted = reverse, deasserted = forward). This pin is driven low to place the channel in the reverse direction. The peripheral is only allowed to drive the bi-directional data bus while in ECP Mode and HostAck is low and nSelectIn is high. Always deasserted in ECP mode. PError (nAckReverse) I Select nAutoFd (HostAck) I O nFault (nPeriphRequest) I nInit O nSelectIn O 98 Register Definitions The register definitions are based on the standard IBM addresses for LPT. All of the standard printer ports are supported. The additional registers attach to an upper bit decode of the standard LPT port definition to avoid conflict with standard ISA devices. The port is equivalent to a generic parallel port interface and may be operated in that mode. The port registers vary depending on the mode field in the ecr. The table below lists these dependencies. Operation of the devices in modes other that those specified is undefined. NAME data ecpAFifo dsr dcr cFifo ecpDFifo tFifo cnfgA cnfgB ecr Table 39 - ECP Register Definitions ADDRESS (Note 1) ECP MODES +000h R/W +000h R/W +001h R/W +002h R/W +400h R/W +400h R/W +400h R/W +400h R +401h R/W +402h R/W 000-001 011 All All 010 011 110 111 111 All FUNCTION Data Register ECP FIFO (Address) Status Register Control Register Parallel Port Data FIFO ECP FIFO (DATA) Test FIFO Configuration Register A Configuration Register B Extended Control Register Note 1: These addresses are added to the parallel port base address as selected by configuration register or jumpers. Note 2: All addresses are qualified with AEN. Refer to the AEN pin definition. Table 40 - Mode Descriptions DESCRIPTION* SPP mode PS/2 Parallel Port mde Parallel Port Data FIFO mode ECP Parallel Port mode EPP mode (If this option is enabled in the configuration registers) (Reserved) Test mode Configuration mode *Refer to ECR Register Description MODE 000 001 010 011 100 101 110 111 99 DATA and ecpAFifo PORT ADDRESS OFFSET = 00H Modes 000 and 001 (Data Port) The Data Port is located at an offset of '00H' from the base address. The data register is cleared at initialization by RESET. During a WRITE operation, the Data Register latches the contents of the data bus on the rising edge of the nIOW input. The contents of this register are buffered (non inverting) and output onto the PD0 - PD7 ports. During a READ operation, PD0 - PD7 ports are read and output to the host CPU. Mode 011 (ECP FIFO - Address/RLE) A data byte written to this address is placed in the FIFO and tagged as an ECP Address/RLE. The hardware at the ECP port transmits this byte to the peripheral automatically. The operation of this register is only defined for the forward direction (direction is 0). Refer to the ECP Parallel Port Forward Timing Diagram, located in the Timing Diagrams section of this data sheet. DEVICE STATUS REGISTER (dsr) ADDRESS OFFSET = 01H The Status Port is located at an offset of '01H' from the base address. Bits 0 - 2 are not implemented as register bits, during a read of the Printer Status Register these bits are a low level. The bits of the Status Port are defined as follows: BIT 3 nFault The level on the nFault input is read by the CPU as bit 3 of the Device Status Register. BIT 4 Select The level on the Select input is read by the CPU as bit 4 of the Device Status Register. BIT 5 PError The level on the PError input is read by the CPU as bit 5 of the Device Status Register. Printer Status Register. BIT 6 nAck The level on the nAck input is read by the CPU as bit 6 of the Device Status Register. BIT 7 nBusy The complement of the level on the BUSY input is read by the CPU as bit 7 of the Device Status Register. DEVICE CONTROL REGISTER (dcr) ADDRESS OFFSET = 02H The Control Register is located at an offset of '02H' from the base address. The Control Register is initialized to zero by the RESET input, bits 0 to 5 only being affected; bits 6 and 7 are hard wired low. BIT 0 STROBE - STROBE This bit is inverted and output onto the nSTROBE output. BIT 1 AUTOFD - AUTOFEED This bit is inverted and output onto the nAUTOFD output. A logic 1 causes the printer to generate a line feed after each line is printed. A logic 0 means no autofeed. BIT 2 nINIT - nINITIATE OUTPUT This bit is output onto the nINIT output without inversion. BIT 3 SELECTIN This bit is inverted and output onto the nSLCTIN output. A logic 1 on this bit selects the printer; a logic 0 means the printer is not selected. BIT 4 ackIntEn - INTERRUPT REQUEST ENABLE The interrupt request enable bit when set to a high level may be used to enable interrupt 100 requests from the Parallel Port to the CPU due to a low to high transition on the nACK input. Refer to the description of the interrupt under Operation, Interrupts. BIT 5 DIRECTION If mode=000 or mode=010, this bit has no effect and the direction is always out regardless of the state of this bit. In all other modes, Direction is valid and a logic 0 means that the printer port is in output mode (write); a logic 1 means that the printer port is in input mode (read). Bits 6 and 7 during a read are a low level, and cannot be written. cFifo (Parallel Port Data FIFO) ADDRESS OFFSET = 400h Mode = 010 Bytes written or DMAed from the system to this FIFO are transmitted by a hardware handshake to the peripheral using the standard parallel port protocol. Transfers to the FIFO are byte aligned. This mode is only defined for the forward direction. ecpDFifo (ECP Data FIFO) ADDRESS OFFSET = 400H Mode = 011 Bytes written or DMAed from the system to this FIFO, when the direction bit is 0, are transmitted by a hardware handshake to the peripheral using the ECP parallel port protocol. Transfers to the FIFO are byte aligned. Data bytes from the peripheral are read under automatic hardware handshake from ECP into this FIFO when the direction bit is 1. Reads or DMAs from the FIFO will return bytes of ECP data to the system. tFifo (Test FIFO Mode) ADDRESS OFFSET = 400H Mode = 110 Data bytes may be read, written or DMAed to or from the system to this FIFO in any direction. Data in the tFIFO will not be transmitted to the to the parallel port lines using a hardware protocol handshake. However, data in the tFIFO may be displayed on the parallel port data lines. The tFIFO will not stall when overwritten or underrun. If an attempt is made to write data to a full tFIFO, the new data is not accepted into the tFIFO. If an attempt is made to read data from an empty tFIFO, the last data byte is reread again. The full and empty bits must always keep track of the correct FIFO state. The tFIFO will transfer data at the maximum ISA rate so that software may generate performance metrics. The FIFO size and interrupt threshold can be determined by writing bytes to the FIFO and checking the full and serviceIntr bits. The writeIntrThreshold can be determined by starting with a full tFIFO, setting the direction bit to 0 and emptying it a byte at a time until This may generate a serviceIntr is set. spurious interrupt, but will indicate that the threshold has been reached. The readIntrThreshold can be determined by setting the direction bit to 1 and filling the empty tFIFO a byte at a time until serviceIntr is set. This may generate a spurious interrupt, but will indicate that the threshold has been reached. 101 Data bytes are always read from the head of tFIFO regardless of the value of the direction bit. For example if 44h, 33h, 22h is written to the FIFO, then reading the tFIFO will return 44h, 33h, 22h in the same order as was written. cnfgA (Configuration Register A) ADDRESS OFFSET = 400H Mode = 111 This register is a read only register. When read, 10H is returned. This indicates to the system that this is an 8-bit implementation. (PWord = 1 byte) cnfgB (Configuration Register B) ADDRESS OFFSET = 401H Mode = 111 BIT 7 compress This bit is read only. During a read it is a low level. This means that this chip does not support hardware RLE compression. It does support hardware de-compression! BIT 6 intrValue Returns the value on the ISA iRq line to determine possible conflicts. BITS 5:0 Reserved During a read are a low level. These bits cannot be written. ecr (Extended Control Register) ADDRESS OFFSET = 402H Mode = all This register controls the extended ECP parallel port functions. BITS 7,6,5 These bits are Read/Write and select the Mode. BIT 4 nErrIntrEn Read/Write (Valid only in ECP Mode) 1: Disables the interrupt generated on the asserting edge of nFault. 0: Enables an interrupt pulse on the high to low edge of nFault. Note that an interrupt will be generated if nFault is asserted (interrupting) and this bit is written from a 1 to a 0. This prevents interrupts from being lost in the time between the read of the ecr and the write of the ecr. BIT 3 dmaEn Read/Write 1: Enables DMA (DMA starts when serviceIntr is 0). 0: Disables DMA unconditionally. BIT 2 serviceIntr Read/Write 1: Disables DMA and all of the service interrupts. 0: Enables one of the following 3 cases of interrupts. Once one of the 3 service interrupts has occurred serviceIntr bit shall be set to a 1 by hardware, it must be reset to 0 to re-enable the interrupts. Writing this bit to a 1 will not cause an interrupt. case dmaEn=1: During DMA (this bit is set to a 1 when terminal count is reached). case dmaEn=0 direction=0: This bit shall be set to 1 whenever there are writeIntrThreshold or more bytes free in the FIFO. case dmaEn=0 direction=1: This bit shall be set to 1 whenever there are readIntrThreshold or more valid bytes to be read from the FIFO. BIT 1 full Read only 1: The FIFO cannot accept another byte or the FIFO is completely full. 0: The FIFO has at least 1 free byte. BIT 0 empty Read only 1: The FIFO is completely empty. 0: The FIFO contains at least 1 byte of data. 102 R/W 000: Table 41 - Extended Control Register MODE Standard Parallel Port mode . In this mode the FIFO is reset and common collector drivers are used on the control lines (nStrobe, nAutoFd, nInit and nSelectIn). Setting the direction bit will not tri-state the output drivers in this mode. PS/2 Parallel Port mode. Same as above except that direction may be used to tri-state the data lines and reading the data register returns the value on the data lines and not the value in the data register. All drivers have active pull-ups (push-pull). Parallel Port FIFO mode. This is the same as 000 except that bytes are written or DMAed to the FIFO. FIFO data is automatically transmitted using the standard parallel port protocol. Note that this mode is only useful when direction is 0. All drivers have active pull-ups (push-pull). ECP Parallel Port Mode. In the forward direction (direction is 0) bytes placed into the ecpDFifo and bytes written to the ecpAFifo are placed in a single FIFOand transmitted automatically to the peripheral using ECP Protocol. In the reverse direction (direction is1) bytes are moved from the ECP parallel port and packed into bytes in the ecpDFifo. All drivers have active pull-ups (push-pull). Selects EPP Mode: In this mode, EPP is selected if the EPP supported option is selected in configuration register CR4. All drivers have active pull-ups (push-pull). Reserved Test Mode. In this mode the FIFO may be written and read, but the data will not be transmitted on the parallel port. All drivers have active pull-ups (push-pull). Configuration Mode. In this mode the confgA, confgB registers are accessible at 0x400 and 0x401. All drivers have active pull-ups (push-pull). 001: 010: 011: 100: 101: 110: 111: 103 OPERATION Mode Switching/Software Control Software will execute P1284 negotiation and all operation prior to a data transfer phase under programmed I/O control (mode 000 or 001). Hardware provides an automatic control line handshake, moving data between the FIFO and the ECP port only in the data transfer phase (modes 011 or 010). Setting the mode to 011 or 010 will cause the hardware to initiate data transfer. If the port is in mode 000 or 001 it may switch to any other mode. If the port is not in mode 000 or 001 it can only be switched into mode 000 or 001. The direction can only be changed in mode 001. Once in an extended forward mode the software should wait for the FIFO to be empty before switching back to mode 000 or 001. In this case all control signals will be deasserted before the mode switch. In an ecp reverse mode the software waits for all the data to be read from the FIFO before changing back to mode 000 or 001. Since the automatic hardware ecp reverse handshake only cares about the state of the FIFO it may have acquired extra data which will be discarded. It may in fact be in the middle of a transfer when the mode is changed back to 000 or 001. In this case the port will deassert nAutoFd independent of the state of the transfer. The design shall not cause glitches on the handshake signals if the software meets the constraints above. ECP Operation Prior to ECP operation the Host must negotiate on the parallel port to determine if the peripheral supports the ECP protocol. This is a somewhat complex negotiation carried out under program control in mode 000. After negotiation, it is necessary to initialize some of the port bits. The following are required: * * * * Set Direction = 0, enabling the drivers. Set strobe = 0, causing the nStrobe signal to default to the deasserted state. Set autoFd = 0, causing the nAutoFd signal to default to the deasserted state. Set mode = 011 (ECP Mode) ECP address/RLE bytes or data bytes may be sent automatically by writing the ecpAFifo or ecpDFifo respectively. Note that all FIFO data transfers are byte wide and byte aligned. Address/RLE transfers are byte-wide and only allowed in the forward direction. The host may switch directions by first switching to mode = 001, negotiating for the forward or reverse channel, setting direction to 1 or 0, then setting mode = 011. When direction is 1 the hardware shall handshake for each ECP read data byte and attempt to fill the FIFO. Bytes may then be read from the ecpDFifo as long as it is not empty . ECP transfers may also be accomplished (albeit slowly) by handshaking individual bytes under program control in mode = 001, or 000. Termination from ECP Mode Termination from ECP Mode is similar to the termination from Nibble/Byte Modes. The host is permitted to terminate from ECP Mode only in specific well-defined states. The termination can only be executed while the bus is in the forward direction. To terminate while the channel is in the reverse direction, it must first be transitioned into the forward direction. 104 Command/Data ECP Mode supports two advanced features to improve the effectiveness of the protocol for some applications. The features are implemented by allowing the transfer of normal 8-bit data or 8-bit commands. When in the forward direction, normal data is transferred when HostAck is high and an 8 bit command is transferred when HostAck is low. The most significant bit of the command indicates whether it is a run-length count (for compression) or a channel address. When in the reverse direction, normal data is transferred when PeriphAck is high and an 8-bit command is transferred when PeriphAck is low. The most significant bit of the command is always zero. Reverse channel addresses are seldom used and may not be supported in hardware. Table 42 Forward Channel Commands (HostAck Low) Reverse Channel Commands (PeripAck Low) D7 D[6:0] 0 1 Data Compression The FDC37C669 supports run length encoded (RLE) decompression in hardware and can transfer compressed data to a peripheral. Run length encoded (RLE) compression in hardware is not supported. To transfer compressed data in ECP mode, the compression count is written to the ecpAFifo and the data byte is written to the ecpDFifo. Compression is accomplished by counting identical bytes and transmitting an RLE byte that indicates how many times the next byte is to be repeated. Decompression simply intercepts the RLE byte and repeats the following byte the specified number of times. When a run-length count is received from a peripheral, the subsequent data byte is replicated the specified number of times. A run-length count of zero specifies that only one byte of data is represented by the next data byte, whereas a run-length count of 127 indicates that the next byte should be expanded to 128 bytes. To prevent data expansion, however, run-length counts of zero should be avoided. Pin Definition The drivers for nStrobe, nAutoFd, nInit and nSelectIn are open-collector in mode 000 and are push-pull in all other modes. ISA Connections The interface can never stall causing the host to hang. The width of data transfers is strictly controlled on an I/O address basis per this specification. All FIFO-DMA transfers are byte wide, byte aligned and end on a byte boundary. (The PWord value can be obtained by reading Configuration Register A, cnfgA, described in the next section). Single byte wide transfers Run-Length Count (0-127) (mode 0011 0X00 only) Channel Address (0-127) 105 are always possible with standard or PS/2 mode using program control of the control signals. Interrupts The interrupts are enabled by serviceIntr in the ecr register. serviceIntr = 1 Disables the DMA and all of the service interrupts. Enables the selected interrupt condition. If the interrupting condition is valid, then the interrupt is generated immediately when this bit is changed from a 1 to a 0. This can occur during Programmed I/O if the number of bytes removed or added from/to the FIFO does not cross the threshold. b. (1) When serviceIntr is 0, dmaEn is 0, direction is 1 and there are readIntrThreshold or more bytes in the FIFO. Also, an interrupt is generated when serviceIntr is cleared to 0 whenever there are readIntrThreshold or more bytes in the FIFO. serviceIntr = 0 3. When nErrIntrEn is 0 and nFault transitions from high to low or when nErrIntrEn is set from 1 to 0 and nFault is asserted. 4. When ackIntEn is 1 and the nAck signal transitions from a low to a high. FIFO Operation The FIFO threshold is set in the chip configuration registers. All data transfers to or from the parallel port can proceed in DMA or Programmed I/O (non-DMA) mode as indicated by the selected mode. The FIFO is used by selecting the Parallel Port FIFO mode or ECP Parallel Port Mode. (FIFO test mode will be addressed separately). After a reset, the FIFO is disabled. Each data byte is transferred by a Programmed I/O cycle or PDRQ depending on the selection of DMA or Programmed I/O mode. The following paragraphs detail the operation of the FIFO flow control. In these descriptions, The interrupt generated is ISA friendly in that it must pulse the interrupt line low, allowing for interrupt sharing. After a brief pulse low following the interrupt event, the interrupt line is tri-stated so that other interrupts may assert. An interrupt is generated when: 1. For DMA transfers: When serviceIntr is 0, dmaEn is 1 and the DMA TC is received. 2. For Programmed I/O: a. When serviceIntr is 0, dmaEn is 0, direction is 0 and there are writeIntrThreshold or more free bytes in the FIFO. Also, an interrupt is generated when serviceIntr is cleared to 0 whenever there are writeIntrThreshold or more free bytes in the FIFO. 106 A high value of threshold (i.e. 12) is used with a "sluggish" system by affording a long latency period after a service request, but results in more frequent service requests. DMA TRANSFERS Note: PDRQ - Currently selected Parallel Port DRQ channel nPDACK - Currently selected Parallel Port DACK channel PINTR - Currently selected Parallel Port IRQ channel Restarting the DMA is accomplished by enabling DMA in the host, setting dmaEn to 1, followed by setting serviceIntr to 0. DMA Mode - Transfers from the FIFO to the Host (Note: In the reverse mode, the peripheral may not continue to fill the FIFO if it runs out of data to transfer, even if the chip continues to request more data from the peripheral.) he ECP activates the PDRQ pin whenever there is data in the FIFO. The DMA controller must respond to the request by reading data from the FIFO. The ECP will deactivate the PDRQ pin when the FIFO becomes empty or when the TC becomes true (qualified by nPDACK), indicating that no more data is required. PDRQ goes inactive after nPDACK goes active for the last byte of a data transfer (or on the active edge of nIOR, on the last byte, if no edge is present on nPDACK). If PDRQ goes inactive due to the FIFO going empty, then PDRQ is active again as soon as there is one byte in the FIFO. If PDRQ goes inactive due to the TC, then PDRQ is active again when there is one byte in the FIFO, and serviceIntr has been re-enabled. (Note: A data underrun may occur if PDRQ is not removed in time to prevent an unwanted cycle.) Programmed I/O Mode or Non-DMA Mode The ECP or parallel port FIFOs may also be operated using interrupt driven programmed I/O. Software can determine the writeIntrThreshold, readIntrThreshold, and FIFO depth by accessing the FIFO in Test Mode. Programmed I/O transfers are to the ecpDFifo at 400H and ecpAFifo at 000H or from the ecpDFifo located at 400H, or to/from the tFifo at 400H. To use the programmed I/O transfers, the host first sets up the direction and state, sets dmaEn to 0 and serviceIntr to 0. DMA transfers are always to or from the ecpDFifo, tFifo or CFifo. DMA utilizes the standard PC DMA services. To use the DMA transfers, the host first sets up the direction and state as in the programmed I/O case. Then it programs the DMA controller in the host with the desired count and memory address. Lastly it sets dmaEn to 1 and serviceIntr to 0. The ECP requests DMA transfers from the host by activating the PDRQ pin. The DMA will empty or fill the FIFO using the appropriate direction and mode. When the terminal count in the DMA controller is reached, an interrupt is generated and serviceIntr is asserted, disabling DMA. In order to prevent possible blocking of refresh requests dReq shall not be asserted for more than 32 DMA cycles in a row. The FIFO is enabled directly by asserting nPDACK and addresses need not be valid. PINTR is generated when a TC is received. PDRQ must not be asserted for more than 32 DMA cycles in a row. After the 32nd cycle, PDRQ must be kept unasserted until nPDACK is deasserted for a minimum of 350nsec. (Note: The only way to properly terminate DMA transfers is with a TC). DMA may be disabled in the middle of a transfer by first disabling the host DMA controller. Then setting serviceIntr to 1, followed by setting dmaEn to 0, and waiting for the FIFO to become empty or full. 107 The ECP requests programmed I/O transfers from the host by activating the PINTR pin. The programmed I/O will empty or fill the FIFO using the appropriate direction and mode. Note: A threshold of 16 is equivalent to a threshold of 15. These two cases are treated the same. Programmed I/O - Transfers from the FIFO to the Host In the reverse direction an interrupt occurs when serviceIntr is 0 and readIntrThreshold bytes are available in the FIFO. If at this time the FIFO is full it can be emptied completely in a single burst, otherwise readIntrThreshold bytes may be read from the FIFO in a single burst. readIntrThreshold = (16- the FIFO. If at this time the FIFO is full, it can be completely emptied in a single burst, otherwise a minimum of (16- An interrupt is generated when serviceIntr is 0 and the number of bytes in the FIFO is greater than or equal to (16- An interrupt is generated when serviceIntr is 0 and the number of bytes in the FIFO is less than or equal to 108 AUTO POWER MANAGEMENT Power management capabilities are provided for the following logical devices: floppy disk, UART 1, UART 2 and the parallel port. For each logical device, two types of power management are provided; direct powerdown and auto powerdown. Direct powerdown is controlled by the powerdown bits in the configuration registers. One bit is provided for each logical device. Auto Powerdown can be enabled for each logical device by setting the Auto Powerdown Enable bit in the configluration registers. In addition, a chip powerdown has been provided by using the POWERGOOD pin. Refer to the description of the POWERGOOD pin for more information. FDC Power Management Direct power management is controlled by bit 3 of Configuration Register 0(CR0). Refer to CR0 bit 3 for more information. Auto Power Management is enabled by CR7 bit 7. When set, this bit allows FDC to enter powerdown when all of the following conditions have been met: 1. 2. The motor enable pins of register DOR (3F2H/372H) are inactive (zero). The part must be idle; MSR=80H and INT = 0 (INT may be high even if MSR = 80H due to polling interrupts). The internal head unload timer must have expired. The Auto powerdown timer (10msec) must have timed out. An internal timer is initiated as soon as the auto powerdown command is enabled. The part is then powered down when all the conditions are met. During the countdown of the powerdown timer, any operation of read MSR or read/write data (FIFO) will reinitiate the timer. Disabling the auto powerdown mode cancels the timer and holds the FDC37C669 out of auto powerdown. DSR From Powerdown If DSR powerdown is used when the part is in auto powerdown, the DSR powerdown will override the auto powerdown. However, when the part is awakened from DSR powerdown, the auto powerdown will once again become effective. Wake Up From Auto Powerdown If the part enters the powerdown state through the auto powerdown mode, then the part can be awakened by reset or by appropriate access to certain registers. If a hardware or software reset is used then the part will go through the normal reset sequence. If the access is through the selected registers, then the FDC37C669 resumes operation as though it was never in powerdown. Besides activating the RESET pin or one of the software reset bits in the DOR or DSR, the following register accesses will wake up the part: 1. Enabling any one of the motor enable bits in the DOR register (reading the DOR does not awaken the part). 2. A read from the MSR register. 3. A read or write to the Data register. 3. 4. 109 Once awake, the FDC37C669 will reinitiate the auto powerdown timer for 10 ms. The part will powerdown again when all the powerdown conditions are satisfied. Register Behavior Table 43 reiterates the AT and PS/2 (including modes 30) configuration registers available. It also shows the type of access permitted. In order to maintain software transparency, access to all the registers must be maintained. As Table 43 shows, two sets of registers are distinguished based on whether their access results in the part remaining in powerdown state or exiting it. Access to all other registers is possible without awakening the part. These registers can be accessed during powerdown without changing the status of the part. A read from these registers will reflect the true status as shown in the register description in the FDC description. A write to the part will result in the part retaining the data and subsequently reflecting it when the part awakens. Accessing the part during powerdown may cause an increase in the power consumption by the part. The part will revert back to its low power mode when the access has been completed. Pin Behavior The FDC37C669 is specifically designed for portable PC systems in which power conservation is a primary concern. This makes the behavior of the pins during powerdown very important. The pins of the FDC37C669 can be divided into two major categories: system interface and floppy disk drive interface. The floppy disk drive pins are disabled so that no power will be drawn through the part as a result of any voltage applied to the pin within the part's power supply range. Most of the system interface pins are left active to monitor system accesses that may wake up the part. System Interface Pins Table 44 gives the state of the system interface pins in the powerdown state. Pins unaffected by the powerdown are labeled "Unchanged". Input pins are "Disabled" to prevent them from causing currents internal to the FDC37C669 when they have indeterminate input values. 110 Table 43 - PC/AT and PS/2 Available Registers Available Registers Base + Address 00H 01H 02H 03H 04H 06H 07H 07H 04H 05H PC-AT ------DOR (1) --DSR (1) --DIR CCR MSR Data PS/2 (Model 30) SRA SRB DOR (1) --DSR (1) --DIR CCR MSR Data Access Permitted R R R/W --W --R W R R/W Access to these registers DOES NOT wake up the part Access to these registers wakes up the part Note 1: Writing to the DOR or DSR does not wake up the part, however, writing any of the motor enable bits or doing a software reset (via DOR or DSR reset bits) will wake up the part. Table 44 - State of System Pins in Auto Powerdown System Pins State in Auto Powerdown IOR IOW A[0:9] D[0:7] RESET IDENT DACK TC FINTR DB[0:7] FDRQ Input Pins Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Output Pins Unchanged (low) Unchanged Unchanged (low) 111 FDD Interface Pins All pins in the FDD interface which can be connected directly to the floppy disk drive itself are either DISABLED or TRISTATED. Pins used for local logic control or part programming are unaffected. Table 47 depicts the state of the floppy disk drive interface pins in the powerdown state. Table 45 - State of Floppy Disk Drive Interface Pins in Powerdown FDD Pins State in Auto Powerdown Input Pins RDATA WP TRK0 INDX DRV2 DSKCHG Output Pins MOTEN[0:3] DS[0:3} DIR STEP WRDATA WE HDSEL DENSEL DRATE[0:1] Tristated Tristated Active Active Tristated Tristated Active Active Active Input Input Input Input Input Input 112 UART Power Management Direct power management is controlled by CR2 bits 3 and 7. Refer to CR2 bits 3 and 7 for more information. Auto Power Management is enabled by CR7 bits 5 and 6. When set, these bit allows the following auto power management operations: 1. The transmitter enters auto powerdown when the transmit buffer and shift register are empty. The receiver enters powerdown when the following conditions are all met: Parallel Port Direct power management is controlled by CR1 bit 2. Refer to CR1 bit 2 for more information. Auto Power Management is enabled by CR7 bit 4. When set, this bit allows the ECP or EPP logical parallel port blocks to be placed into powerdown when not being used. The EPP logic is in powerdown under any of the following conditions: 1. EPP is not enabled in the configuration registers. EPP is not selected through ecr while in ECP mode. 2. 2. a. b. Note: Receive FIFO is empty The receiver is waiting for a start bit. While in powerdown the Ring Indicator interrupt is still valid and transitions when the RI input changes. The ECP logic is in powerdown under any of the following conditions: 1. ECP is not enabled in the configuration registers. SPP, PS/2 Parallel port or EPP mode is selected through ecr while in ECP mode. Exit Auto Powerdown 2 The transmitter exits powerdown on a write to the XMIT buffer. The receiver exits auto powerdown when RXDx changes state. Exit Auto Powerdown The parallel port logic can change powerdown modes when the ECP mode is changed through the ecr register or when the parallel port mode is changed through the configuration registers. 113 INTEGRATED DRIVE ELECTRONICS INTERFACE The IDE interface enables hard disks with embedded controllers (AT and XT) to be interfaced to the host processor. The following definitions are for reference only. These registers are not implemented in the FDC37C669. Access to these registers is controlled by the FDC37C669. For more information, refer to the IDE pin descriptions and the ATA specification. HOST FILE REGISTERS The HOST FILE REGISTERS are accessed by the AT Host, rather than the Local Processor. There are two groups of registers, the AT Task File, and the Miscellaneous AT Registers. REGISTER ADDRESS (CR21) IDE BASE I/O ADDRESS +[0:7] (CR22) BASE I/O ADDRESS +6 TASK FILE REGISTERS MISC AT REGISTER ADDRESS (CR21) Base +[0:7] These AT registers contain the Task File Registers. These registers communicate data, command, and status information with the AT host, and are addressed when nHDCS0 is low. ADDRESS (CR22) Base +6 This AT register may be used by the BIOS for drive control. It is accessed by the AT interface when nHDSC1 is active. Figure 2 shows the AT Host Register Map of the FDC37C669. FIGURE 2 - HOST PROCESSOR REGISTER ADDRESS MAP (AT MODE) TASK FILE REGISTERS Task File Registers may be accessed by the host AT when pin nHDCS0 is active (low). The Data Register (1F0H) is 16 bits wide; the remaining task file registers are 8 bits wide. The task file registers are ATA and EATA compatible. Please refer to the ATA and EATA specifications. These are available from: Global Engineering 2805 McGaw Street Irvine, CA 92714 (800) 854-7179 (714) 261-1455 114 COMMAND RESTORE (RECALIBRATE) SEEK READ SECTOR WRITE SECTOR FORMAT TRACK READ VERIFY DIAGNOSE SET PARAMETERS Bit definitions: D7 0 0 0 0 0 0 1 1 D6 0 1 0 0 1 1 0 0 D5 0 1 1 1 0 0 0 0 D4 1 1 0 1 1 0 1 1 D3 r r D D D D 0 0 D2 r r 0 0 0 0 0 0 D1 r r L L 0 0 0 0 D0 r r T T 0 T 0 1 r: specifies the step rate to be used for the command. D: If set, 16 bit DMA is to be used for the data transfer. (Optional for high performance) L: If set, the ECC will be transferred following the data. T: if set, retries are inhibited for the command. 115 AT HOST ADDRESSABLE REGISTERS (For Reference Only) TASK FILE REGISTERS ADDR 000H R/W D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NAME DATA REG DATA REGISTER (REDIRECTED TO FIFO) ADDR 001H 001H R/W R W D7 BB D6 CRC D5 - D4 ID D3 - D2 AC D1 TK D0 DM NAME ERROR FLAGS WRITE PRECOMP CYLINDER CYLINDER NUMBER +4 002H 116 003H 004H 005H 006H 007H 007H R/W R/W R/W R/W R/W R W BSY RDY NUMBER OF SECTORS SECTOR NUMBER CYLINDER NUMBER (LSB's) CYLINDER NUMBER (MSB's) DRIVE WF SC DRQ HEAD CD INDEX SECTOR COUNT SECTOR NUMBER CYLINDER LOW CYLINDER HIGH HEAD, DRIVE ERR STATUS COMMAND COMMAND MISCELLANEOUS AT REGISTERS ADDR 3F6H/3 76H 3F6H/3 76H 3F7H/3 77H 3F7H/3 77H 117 R/W R W D7 BSY D6 RDY D5 WF D4 SC D3 DRQ HS3EN D2 CD ADPTR RESET D1 INDEX DISABLE IRQ D0 ERR RESERVED NAME ERROR FLAGS FIXED DISK RESERVED R W - nWG - nHS3 - nHS2 - nHS1 - nHS0 - nDS1 - nDS0 - DIGITAL INPUT RESERVED CONFIGURATION The configuration of the chip is programmable through software selectable configuration registers. CONFIGURATION REGISTER ADDRESS The address at which the Configuration Registers are located is controlled by the nRTS2 pin. The state of the nRTS2 pin is latched by the trailing edge of hardware reset. If this latched state is a 0, the Configuration Registers are located at address 3F0H-3F1H. If the latched state is a 1, then the Configuration Registers are located at address 370H-371H. CONFIGURATION REGISTERS The configuration registers are used to select programmable options of the chip. After power up, the chip is in the default mode. The default modes are identified in the Configuration Mode Register Description. To program the configuration registers, the following sequence must be followed: 1. 2. 3. Enter Configuration Mode. Configure the Configuration Registers. Exit Configuration Mode. Enter Configuration Mode To enter the configuration mode, two writes in succession to port 3F0H (or 370H) with 55H data are required. If a write to another address or port occurs between these two writes, the chip does not enter the configuration mode. It is strongly recommended that interrupts be disabled for the duration of these two writes. Configuration Mode The chip contains configuration registers CR00-CR29. These registers are accessed by first writing the number (0-29H) of the desired register to port 3F0H (or 370H) and then writing or reading the configuration register through port 3F1H (or 371H). Exit Configuration Mode The configuration mode is exited by writing an AAH to port 3F0H (or 370H). Programming Example The following is an example of a configuration program in Intel 8086 assembly language. 118 ;-----------------------------. ; ENTER CONFIGURATION MODE | ;-----------------------------' MOV DX,3F0H MOV AX,055H ; CLI ; disable interrupts OUT DX,AL OUT DX,AL STI ; enable interrupts ;-----------------------------. ; CONFIGURE REGISTERS CR0-CRx | ;-----------------------------' MOV DX,3F0H MOV AL,00H OUT DX,AL ; Point to CR0 MOV DX,3F1H MOV AL,3FH OUT DX,AL ; Update CR0 ; MOV DX,3F0H ; MOV AL,01H OUT DX,AL ; Point to CR1 MOV DX,3F1H MOV AL,9FH OUT DX,AL ; Update CR1 ; ; Repeat for all CRx registers ; ;-----------------------------. ; EXIT CONFIGURATION MODE | ;-----------------------------' MOV DX,3F0H MOV AX,0AAH OUT DX,AL 119 Table 46 - Configuration Registers Default 28H 9CH 88H 78H CR00 CR01 CR02 CR03 DB7 Valid Lock CRx UART2 PWR ADRX/ DRV2/ IRQ_B 00H 00H FFH 00H 00H 00H 00H 00H 00H CR04 CR05 CR06 CR07 CR08 CR09 CR0A CR0B CR0C FDD3-DRTx UART 2 Speed UART 1 Speed Device ID Device Revision Test 7 IR_Test Test 6 PLL_Clk Test 5 AceStop Test 4 Pll Stop Test 3 Pll Gain Reserved GAMECS - ADR[9:4] FDD3-DTx FDD2-DTx FDC - ADR[9:4] IDE - nHDCS0 - ADR[9:4] IDE - nHDCS1 - ADR[9:4] Parallel Port - ADR[9:2] Serial Port 1 - ADR[9:3] Serial Port 2 - ADR[9:3] FDC DRQ FDC IRQ Serial 1 IRQ Reserved Parallel Port DRQ Parallel Port IRQ Serial 2 IRQ IRQIN IRQ 0 0 FDD1-DTx 0 0 0 GAMECS Config FDD0-DTx 0 0 1 Test 2 Test 1 Reserved Test 10ms IR loop Back Test 0 ADRA7 ALT I/O Reserved EPP Type EXTx4 MIDI 2 DRV 0X1 Floppy Drive C ADRA5 ADRA4 Reserved Reserved FDD2-DRTx UART 2 Mode MIDI 1 DEN SEL IDENT DB6 DB5 Reserved Reserved Reserved MFM DRVDEN 1 DB4 DB3 FDC PWR PP MODE UART1 PWR Reserved ADRX/ DRV2/ IRQ_B Parallel Port FDC DMA Mode Floppy Drive B Reserved 0 0 ADRA10 FDD1-DRTx UART 2 Duplex PP Ext. Modes Reserved Floppy Drive A Floppy Boot Drive 0 ADRA9 0 ADRA8 Enhanced FDC Mode 2 PWRGD/ GAMECS DB2 Reserved PP PWR DB1 IDE EN Reserved Reserved DB0 Floppy Drive D ARDA6 Auto Power Management ADRx Config ECP FIFO Threshold FDD0-DRTx UART 2 XMIT Polarity UART 2 RCV Polarity 03H 02H 00H 00H 00H 00H 3CH 00H 3CH 3CH 3DH 00H 00H 00H 00H 00H 00H 00H CR0D CR0E CR0F CR10 CR11 CR12CR1D CR1E CR1F CR20 CR21 CR22 CR23 CR24 CR25 CR26 CR27 CR28 CR29 Reserved 120 Configuration Register Description The configuration registers consist of the Configuration Select Register (CSR) and Configuration Registers CR-00 -CR-29. The configuration select register is written to by writing to port 3F0H (or 370H). The Configuration Registers CR-00; CR-29 are accessed by reading or writing to port 3F1H (or 371H). Configuration Select Register (CSR) This register can only be accessed when the chip is in the Configuration Mode. This register, located at port 3F0H (370H), must be initialized upon entering the Configuration Mode before the configuration registers can be accessed and is used to select which of the Configuration Registers are to be accessed at port 3F1H (371H). Configuration Registers CR00 -CR29 These registers are set to their default values at power up and are not affected by RESET (except where explicitly defined that a hardware reset causes that bit to be reset to default). They are accessed at port 3F1H (or 371H). Refer to the following descriptions for the function of each configuration register. CR00 This register can only be accessed when the chip is in the Configuration Mode and after the CSR has been initialized to 00H. The default value of this register after power up is 28H. Table 47 - CR00 BIT NO. 0, 1 BIT NAME IDE ENABLE/ Alternate Function DESCRIPTION Bits (Note 1) 10 00 - IDE, IRRX2, IRTX2, IRQ_H disabled (Default) 01 - Reserved (IDE, IRRX2, IRTX2, IRQ_H disabled) 10 - IDE Enabled 11 - IRRX2, IRTX2, IRQ_H Enabled Read only. Read as 0 A high level on this bit, supplies power to the FDC (default). A low level on this bit puts the FDC in low power mode. Read only. A read returns bit 5 as a 1 and bits 4 and 6 as a 0. A high level on this software controlled bit can be used to indicate that a valid configuration cycle has occurred. The control software must take care to set this bit at the appropriate times. Set to zero after power up. This bit has no effect on any other hardware in the chip. 2 3 4,5,6 7 Reserved FDC Power (see note _PWRDN) Reserved Valid Note 1: When "0x" is selected, 30ua pull-ups are active on the "nIDEEN, nHDCS0 and nHDCS1 pins", at all other times, the pull-ups are disabled. When "11" is selected, IRQ_H is available as an IRQ output, and IRRX2 and IRTX2 are available as alternate IR pins (pull-ups disabled). When "10" is selected, nIDEEN, nHDCS0 and nHDCS1 are used to control the IDE interface (pull-ups disabled). 121 CR01 This register can only be accessed in the Configuration Mode and after the CSR has been initialized to 01H. The default value of this register after power up is 9CH. Table 48 - CR01 BIT NO. 0,1 2 BIT NAME Reserved Parallel Port Power (see note _PWRDN) Parallel Port Mode Reserved Reserved Lock CRx DESCRIPTION Read Only. A read returns a 0. A high level on this bit, supplies power to the Parallel Port (Default). A low level on this bit puts the Parallel Port in low power mode. Parallel Port Mode. A high level on this bit, sets the Parallel Port for Printer Mode (Default). A low level on this bit enables the Extended Parallel port modes. Refer to Bits 0 and 1 of CR4 Read Only. A read returns a 1. Read Only. A read returns a 0. A high level on this bit enables the reading and writing of CR00CR18 (Default). A low level on this bit disables the reading and writing of CR0-CRF. Once set to 0, this bit can only be set to 1 by a hard reset or power-up reset. initialized to 02H. The default value of this register after power up is 88H. 3 4 5,6 7 CR02 This register can only be accessed in the Configuration Mode and after the CSR has been Table 49 - CR02 BIT NO. 0:2 3 BIT NAME Reserved UART1 Power down (see note _PWRDN) Reserved UART2 Power down DESCRIPTION Read Only. A read returns a 0. A high level on this bit, allows normal operation of the Primary Serial Port (Default). A low level on this bit places the Primary Serial Port into Power Down Mode. Read Only. A read returns a 0. A high level on this bit, allows normal operation of the Secondary Serial Port (Default). A low level on this bit places the Secondary Serial Port into Power Down Mode. 4:6 7 Note_PWRDN: Power Down bits disable the respective logical device and associated pins, however the power down bit does not disable the selected address range registers for the logical device. To disable the host address registers the logical device's base address must be set below 100h. Therefore devices which are powered down, but still reside at a valid I/O base address will participate in Plug-and-Play range checking. 122 CR03 This register can only be accessed in the Configuration Mode and the CSR has been initialized to 03H. The default value after power up is 780H. Table 50 - CR03 BIT NO. 0 BIT NAME PWRGD/ GAMECS Enhanced Floppy Mode 2 Bit 0 0 1 Bit 1 DESCRIPTION Pin function PWRGD (default) GAMECS Floppy Mode - Refer to the description of the TAPE DRIVE REGISTER (TDR) for more information on these modes. NORMAL Floppy Mode (Default) Enhanced Floppy Mode 2 (OS2) 1 0 1 3 4 Reserved DRVDEN1 Reserved - Read as zero Bit 4 Pin DRVDEN1 output 0 DRVDEN 1 output 1 DRVDEN 1 high (default) IDENT is used in conjunction with MFM to define the interface mode of operation MODE MFM IDENT AT Mode (Default) 1 1 Reserved 0 1 PS/2 1 0 Model 30 0 0 Bit - 7 Bit - 2 Pin 94 0 x DRV2 (input) 1 0 ADRX 1 1 IRQ_B 5 6 MFM IDENT 7,2 ADRx/ DRV2 EN/ IRQ_B 123 CR04 This register can only be accessed in the Configuration Mode and the CSR has been initialized to 04H. The default value after power up is 00H. BIT NO. 1,0 Table 51 - CR04 - Parallel and Serial Extended Setup Register BIT NAME DESCRIPTION Parallel Port Extended Modes Bit 1 0 0 1 1 Bit 0 0 1 0 1 If CR1 bit 3 is a low level then: Standard and Bidirectional Modes (SPP) (Default) EPP Mode and SPP ECP Mode (Note CR4_2) ECP Mode & EPP Mode (Note CR4_1, 2) 2,3 Parallel Port FDC Refer to Parallel Port Floppy Disk Controller description. Bit 3 0 0 1 1 Bit 2 0 1 0 1 Normal PPFD1 PPFD2 Reserved 4 MIDI 1 Serial Clock Select Port 1: A low level on this bit, disables MIDI support, clock = divide by 13 (Default). A high level on this bit enables MIDI support, clock = divide by 12. (Note CR4_3) Serial Clock Select Port 2: A low level on this bit, disables MIDI support, clock = divide by 13 (Default). A high level on this bit enables MIDI support, clock = divide by 12. (Note CR4_3) 0 = EPP 1.9 (Default) 1 = EPP 1.7 1 = use pins IRRX2, IRTX2 (pins 25, 26) 0 = use pins IRRX, IRTX (Default) (pins 88, 89) note: If this bit is set, the Infrared receive and transmit functions will not be available on pins 25 and 26 unless bits [0,1] of CR00 are set to [1,1]. 5 MIDI 2 6 7 EPP Type ALT I/O Note CR4_1: Note CR4_2: Note CR4_3: In this mode, EPP can be selected through the ecr register of ECP as mode 100. In these modes, 2 drives can be supported directly, 3 or 4 drives must use external 4 drive support. SPP can be selected through the ecr register of ECP as mode 000. MIDI Support: The Musical Instrumental Digital Interface (MIDI) operates at 31.25Kbaud (+/-1%) which can be derived from 125KHz. (24MHz/12=2MHz, 2MHz/16=125kHz). 124 CR05 This register can only be accessed in the Configuration Mode and the CSR has been initialized to 05H. The default value after power up is 00H. BIT NO. 0,1 2 Table 52 - CR05- Floppy Disk and IDE Extended Setup Register BIT NAME DESCRIPTION Reserved FDC DMA Mode Read Only. A read returns a 0. 0=(default) Burst mode is enabled for the FDC FIFO execution phase data transfers. 1=Non-Burst mode enabled. The FDRQ and FIRQ pins are strobed once for each byte transferred while the FIFO is enabled. Bit 4 0 0 1 1 Bit 3 0 1 0 1 Densel output Normal (Default) Reserved 1 0 4,3 DenSel 5 6 7 Swap Drv 0,1 EXTx4 Reserved A high level on this bit, swaps drives and motor sel 0 and 1 of the FDC. A low level on this bit does not (Default). External 4 drive support: 0=Internal 2 drive decoder (default). 1=External 4 drive decoder (External 2 to 4 decoder required). Read Only. A read of this bit returns a 0 of this register after power up is FFH. This register holds the floppy disk drive types for up to four floppy disk drives. CR06 This register can only be accessed in the Configuration Mode and after the CSR has been initialized to 06H. The default value 125 CR07 This register can only be accessed in the Configuration Mode and after the CSR has been initialized to 07H. The default value of this register after power up is 00H. This register holds the value for the auto power management, and floppy boot drive. Table 53 - CR07 BIT NO. 0,1 BIT NAME Floppy Boot DESCRIPTION This bit is used to define the boot floppy. 0 = Drive A (default) 1 = Drive B Read as 0. Read as 0. This bit controls the AUTOPOWER DOWN feature of the Parallel Port. The function is: 0 = Auto powerdown disabled (default) 1 = Auto powerdown enabled This bit is reset to the default state by POR or a hardware reset. 2 3 4 Reserved Reserved Parallel Port Enable 5 UART 2 Enable This bit controls the AUTOPOWER DOWN feature of the UART2. The function is: 0 = Auto powerdown disabled (default) 1 = Auto powerdown enabled This bit is reset to the default state by POR or a hardware reset. UART 1 Enable This bit controls the AUTOPOWER DOWN feature of the UART1. The function is: 0 = Auto powerdown disabled (default) 1 = Auto powerdown enabled This bit is reset to the default state by POR or a hardware reset. Floppy Disk Enable This bit controls the AUTOPOWER DOWN feature of the Floppy Disk. The function is: 0 = Auto powerdown disabled (default) 1 = Auto powerdown enabled This bit is reset to the default state by POR or a hardware reset. 6 7 126 CR08 This register can only be accessed in the Configuration Mode and after the CSR has been initialized to 08H. The default value of this register after power up is 00H. This is the lower 4 bits (ADRA7:4) for the ADRx address decode. The non-programmable address bits 3:0 default to 0000b. CR09 This register can only be accessed in the Configuration Mode and after the CSR has been initialized to 09H. The default value of this register after power up is 00H. This is the upper 3 bits (ADRA10:8) (D2 - MSB, D0 - LSB) for the ADRx address decode. ADRx Config (bits 7:6) define the configuration of the ADRx decoder as follows: ADRx Configuration ADRx disabled 1 Byte decode A[3:0]=0000b 8 Byte block decode A[3:0]=0XXXb 16 byte block decode A[3:0]=XXXXb D7 0 0 1 1 D6 0 1 0 1 Upper Address Decode requirements : nCS='0' is required to qualify the ADRx output. CR0A This register can only be accessed in the Configuration Mode and after the CSR has been initialized to 0AH. The default value of this register after power up is 00H. This byte defines the FIFO threshold for the ECP mode parallel port. D7 D6 D5 Table 54 - CR0A D4 D3 THR3 D2 THR2 D1 THR1 D0 THR0 RESERVED - READ ONLY 0 HEX ECP F I F O T H R E S H O L D CR0B This register can only be ac1cessed in the Configuration Mode and after the CSR has been initialized to 0BH. The default value of this register after power up is 00H. This register indicates the data rate table used for each drive. Refer to CR1F for Drive Type register. Table 55 - CR0B FDD3 D7 DRT1 D6 DRT0 D5 DRT1 FDD2 D4 DRT0 D3 DRT1 FDD1 D2 DRT0 D1 DRT1 FDD0 D0 DRT0 127 CR0C This register can only be accessed in the Configuration Mode and after the CSR has been initialized to 0CH. The default value of this register after power up is 00H. This register controls the operating mode of the UART. This register is reset to the default state by a POR or a hardware reset. Table 56 - CR0C BIT NO. 0 1 2 BIT NAME UART 2 RCV Polarity UART 2 XMIT Polarity DESCRIPTION 1 = RX input inverted. 0 = RX input non - inverted (default). 1 = TX output inverted. 0 = TX output non - inverted (default). UART 2 Duplex This bit is used to define the FULL/HALF DUPLEX operation of UART 2. 1 = Half duplex 0 = Full duplex (default) UART 2 MODE UART 2 Mode 543 0 0 0Standard (default) 0 0 1IrDA (HPSIR) 0 1 0Amplitude Shift Keyed IR @ 500Khz 0 1 1Reserved 1 x xReserved UART 1 Speed This bit enables the high speed mode of UART 1 = High speed enabled 0 = Standard (default) UART Speed This bit enables the high speed mode of UART 1 = High speed enabled 0 = Standard (default) 3, 4, 5 6 7 CR0D This register can only be accessed in the Configuration Mode and after the CSR has been initialized to 0DH. This register is read only. This is the Device ID. The default value of this register after power up is 03H. CR0E This register can only be accessed in the Configuration Mode and after the CSR has been initialized to 0EH. This register is read only. The default value of this register after power up is 02H. This is used to identify the chip revision level. 128 CR0F This register can only the Configuration Mode be accessed in and after the CSR has been initialized to 0FH. The default value of this register after power up is 00H. BIT NO. 0 1 2 3 4 5 6 7 Table 57 - CR0F BIT NAME Test 0 Test 1 Test 2 Test 3 Test 4 Test 5 Test 6 Test 7 DESCRIPTION Reserved - Set to zero Reserved - Set to zero Reserved - Set to zero Reserved - Set to zero Reserved - Set to zero Reserved - Set to zero Reserved - Set to zero Reserved - Set to zero 129 CR10 This register can only be accessed in the Configuration Mode and after the CSR has been initialized to 10H. The default value of this register after power up is 00H. BIT NO. 0-2 3 BIT NAME Reserved Pll Gain Table 58 - CR10 DESCRIPTION Reserved - READ ONLY. A read returns a 0. This bit controls the gain of the frequency multiplying phase lock loops. When a 0 (default) the gain is set to a value expected for 5 volt operation. When set to a 1 the gain is doubled to a value for possible 3 volt operation. A 1 in this bit position stops the frequency multiplying phase lock loops. A 0 (default) allows normal operation. This bit when set to a 1 will inhibit the 24MHz clock to the divide by 12/13 that generates the UART clocks, and reset those dividers. When at a 0 (default) these dividers and clocks are enabled. This bit enables the PLL clock generator to run with either a 14.318MHz or 24MHz input clock. A 0 enables the 14.318MHz clock (default), a 1 enables the 24MHz clock. This bit enables the IR test mode. When this bit is set to a 1 the serial data seen by UART RX and TX ports is output on SOUT. A 0 gives normal operation (default). been initialized to 11H. The default value of this register after power up is 00H. 4 5 Pll Stop ACE_STOP 6 PLL Clock Control Infra Red Test 7 CR11 This register can only be accessed in the Configuration Mode and after the CSR has BIT NO. 0 1 2-7 BIT NAME IR Loop Back Test 10ms Reserved Table 59 - CR11 DESCRIPTION When a 1 the IROUT is looped back internally to the IRIN input. When a 0 (default) normal operation. This bit when a 1 tests the 10ms timeout of the FDC autopower down mode. A 0 (default) allows normal operation. Reserved - READ ONLY. A read returns a 0. 130 CR12-CR1D These registers are reserved. The default value of these registers after power up is 00H. CR1E This register can only be accessed in the Configuration Mode and after the CSR has been DB7 ADR9 DB6 ADR8 DB5 ADR7 DB4 ADR6 initialized to 1EH. The default value of this register after power up is 80H. This register is used to select the base address of the Game Chip Select decoder (GAMECS). The GAMECS can be set to 48 locations, on 16 byte boundaries from 100H-3F0H. To disable the GAMECS, set DB1 and DB0 to zero. DB3 ADR5 DB2 ADR4 DB1 DB0 GAMECS Config DB1 0 0 1 1 DB0 0 1 0 1 GAMECS Configuration GAMECS disabled 1 Byte decode, ADR[3:0] = 0001b 8 Byte block decode, ADR[3:0] = 0XXXb 16 byte block decode, ADR[3:0] = XXXXb Upper Address Decode requirements: nCS='0' and A10='0' are required to qualify the GAMECS output. CR03, bit DB0 is the PWRGD/GAMECS control bit and overrides the selection made by the above configuration. 131 CR1F This register can only be accessed in the Configuration Mode and after the CSR has been initialized to 1FH. The default value FDD3 D7 DT0 D6 DT1 D5 DT0 FDD2 D4 DT1 of this register after power up is 00H. This register indicates the Drive Type used for each drive. Refer to CR0B for Data Rate Table register. FDD1 D3 DT0 D2 DT1 D1 DT0 FDD0 D0 DT1 DTx = Drive Type select DRVDEN0 DT0 0 0 DT1 (Note) DENSEL DRVDEN1 (Note) DRATE0 Drive Type 4/2/1 MB 3.5" 2/1 MB 5.25" FDDS 2/1.6/1 MB 3.5" (3-MODE) PS/2 0 1 1 Note: 1 0 1 DRATE1 nDENSEL DRATE0 DRATE0 DRATE0 DRATE1 DENSEL, DRATE1 and DRATE0 map onto two output pins DRVDEN0 and DRVDEN1. be set to 48 locations, on 16 byte boundaries from 100H-3F0H. To disable the FDC, set ADR9 and ADR8 to zero. Upper Address Decode requirements: nCS='0' and A10='0' are required to access the FDC registers. A[3:0] are decoded as 0XXXb. DB3 ADR5 DB2 ADR4 DB1 0 DB0 0 CR20 This register can only be accessed in the Configuration Mode and after the CSR has been initialized to 20H. The default value of this register after power up is 3CH. This register is used to select the base address of the floppy disk controller (FDC). The FDC can DB7 ADR9 DB6 ADR8 DB5 ADR7 DB4 ADR6 132 CR21 This register can only be accessed in the Configuration Mode and after the CSR has been initialized to 21H. The default value of this register after power up is 3CH. This register is used to select the base address of the IDE Interface Control Registers (0-7). This DB7 ADR9 DB6 ADR8 DB5 ADR7 DB4 ADR6 can be set to 48 locations, on 16 byte boundaries from 100H-3F0H. To disable this decode, set ADR9 and ADR8 to zero. Upper Address Decode requirements : nCS='0' and A10='0' are required to access the IDE registers. A[3:0] are decoded as 0XXXb. DB3 ADR5 DB2 ADR4 DB1 0 DB0 0 CR22 This register can only be accessed in the Configuration Mode and after the CSR has been initialized to 22H. The default value of this register after power up is 3DH. This register is used to select the base address of the IDE Interface Alternate Status Register. This can be set to 48 locations, on 16 byte DB7 ADR9 DB6 ADR8 DB5 ADR7 DB4 ADR6 boundaries+6 from 106H-3F6H. To disable this decode, set ADR9 and ADR8 to zero. Upper Address Decode requirements: nCS='0' and A10='0' are required to access the IDE Alternate Status register. A[3:0] must be 0110b. DB3 ADR5 DB2 ADR4 DB1 0 DB0 1 CR23 This register can only be accessed in the Configuration Mode and after the CSR has been initialized to 23H. The default value of this register after power up is 00H. This register is used to select the base address of the parallel port. If EPP is not enabled, the parallel port can be set to 192 locations, on 4 byte boundaries from 100H-3FCH. If EPP is enabled, the DB7 ADR9 DB6 ADR8 DB5 ADR7 EPP Enabled No Yes DB4 ADR6 parallel port can be set to 96 locations, on 8 byte boundaries from 100H-3F8H. To disable the parallel port, set ADR9 and ADR8 to zero. Upper Address Decode requirements: nCS='0' and A10='0' are required to access the Parallel Port when in Compatible, Bi-directional, or EPP modes (A10 is active when in ECP mode). DB3 ADR5 DB2 ADR4 DB1 ADR3 DB0 ADR2 Addressing (low bits) Decode A[1:0] = XXb A[2:0] = XXXb 133 CR24 This register can only be accessed in the Configuration Mode and after the CSR has been initialized to 25H. The default value of this register after power up is 00H. This register is used to select the base address of UART1 (serial port 1). The serial port can be set to 96 DB7 ADR9 DB6 ADR8 DB5 ADR7 DB4 ADR6 locations, on 8 byte boundaries from 100H3F8H. To disable the serial port, set ADR9 and ADR8 to zero. Upper Address Decode requirements : nCS='0' and A10='0' are required to access UART1 registers. A[2:0] are decoded as XXXb. DB3 ADR5 DB2 ADR4 DB1 ADR3 DB0 0 CR25 This register can only be accessed in the Configuration Mode and after the CSR has been initialized to 25H. The default value of this register after power up is 00H. This register is used to select the base address of UART2 (serial port 2). The serial port can be set to 96 DB7 ADR9 DB6 ADR8 DB5 ADR7 DB4 ADR6 locations, on 8 byte boundaries from 100H3F8H. To disable the serial port, set ADR9 and ADR8 to zero. Upper Address Decode requirements : nCS='0' and A10='0' are required to access UART2 registers. A[2:0] are decoded as XXXb. DB3 ADR5 DB2 ADR4 DB1 ADR3 DB0 0 CR26 This register can only be accessed in the Configuration Mode and after the CSR has been initialized to 26H. The default value of this D3-D0 D7-D4 0000 0001 0010 0011 register after power up is 00H. This register is used to select the DMA for the FDC (Bits 4:7) and the parallel port (bits 3:0). Any unselected DMA REQ output is in tristate. DMA Selected None DMA_A DMA_B DMA_C 134 CR27 This register can only be accessed in the Configuration Mode and after the CSR has been initialized to 27H. The default value of this register after power up is 00H. This register is used to select the IRQ for the FDC (Bits 4:7) and the parallel port (bits 3:0). Any unselected IRQ output (registers CR27-CR29) is in tristate. CR28 This register can only be accessed in the Configuration Mode and after the CSR has been initialized to 28H. The default value of this register after power up is 00H. This register is D3-D0 or D7-D4 0000 0001 0010 0011 0100 0101 0110 0111 1000 CR29 This register can only be accessed in the Configuration Mode and after the CSR has been initialized to 29H. The default value of this register after power up is 00H. This register is used to select the IRQ for serial port 1 (bits 7:4) and for serial port 2 (bits 3:0). Refer to IRQ Table for CR27. Any unselected IRQ output (registers CR27 - CR29) is in tristate. To properly share an IRQ among UART1 and UART2: 1) Configure UART1 to use the desired IRQ pin. 2) Set UART2 to 0Fh i.e., set CR28 bits[3:0]=1111. This selects the share IRQ mechanism. Refer to Table 60 on the following page: IRQ Selected None IRQ_A IRQ_B IRQ_C IRQ_D IRQ_E IRQ_F Reserved IRQ_H used to select the IRQ for IRQIN (bits 3:0). Refer to IRQ Table for CR27. Bits 7:4 are reserved and return zero when read. Any unselected IRQ output (registers CR27-CR29) is in tristate. 135 Table 60 - UART Interrupt Operation Table UART1 UART1 UART1 IRQ OUT2 bit Output State 0 Z 1 asserted 1 de-asserted 0 Z 0 Z 1 asserted 1 asserted 1 de-asserted 1 de-asserted 0 Z 1 asserted 1 de-asserted 0 Z 0 Z 1 asserted 1 asserted 1 de-asserted 1 de-asserted UART2 OUT2 bit 0 0 0 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 UART2 UART2 IRQ Output State Z Z Z asserted de-asserted asserted de-asserted asserted de-asserted Z Z Z asserted de-asserted asserted de-asserted asserted de-asserted IRQ PINS UART1 UART2 Pin State Pin State Z Z 1 Z 0 Z Z 1 Z 0 1 1 1 0 0 1 0 0 Z Z 1 Z 0 Z 1 Z 0 Z 1 Z 1 Z 1 Z 0 Z Share IRQ No No No No No No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes It is the responsibility of the software to ensure that two IRQ's are not set to the same IRQ number. Potential damage to chip may result. 136 OPERATIONAL DESCRIPTION MAXIMUM GUARANTEED RATINGS* Operating Temperature Range......................................................................................... 0 C to +70 C o o Storage Temperature Range .......................................................................................... -55 to +150 C o Lead Temperature Range (soldering, 10 seconds) .................................................................... +325 C Positive Voltage on any pin, with respect to Ground ............................................................... VCC+0.3V Negative Voltage on any pin, with respect to Ground.................................................................... -0.3V Maximum VCC ................................................................................................................................ +7V *Stresses above those listed above could cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other condition above those indicated in the operation sections of this specification is not implied. Note: When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes on their outputs when the AC power is switched on or off. In addition, voltage transients on the AC power line may appear on the DC output. If this possibility exists, it is suggested that a clamp circuit be used. DC ELECTRICAL CHARACTERISTICS (TA = 0C - 70C, Vcc = 5 V 10%) TYP MAX UNITS PARAMETER SYMBOL MIN I Type Input Buffer Low Input Level High Input Level IS Type Input Buffer Low Input Level High Input Level Schmitt Trigger Hysteresis ICLK Input Buffer Low Input Level High Input Level VILCK VIHCK 3.0 0.4 V V VILIS VIHIS VHYS 2.2 250 0.8 V V mV Schmitt Trigger Schmitt Trigger VILI VIHI 2.0 0.8 V V TTL Levels o o COMMENTS 137 PARAMETER Input Leakage (All I and IS buffers except PWRGD) Low Input Leakage High Input Leakage Input Current PWRGD I/O24 Type Buffer Low Output Level High Output Level Output Leakage O24 Type Buffer Low Output Level High Output Level Output Leakage OD48 Type Buffer Low Output Level Output Leakage O24P Type Buffer Low Output Level High Output Level Output Leakage 04 Type Buffer Low Output Level High Output Level Output Leakage SYMBOL MIN TYP MAX UNITS COMMENTS IIL IIH IOH -10 -10 75 +10 +10 150 A A A VIN = 0 VIN = VCC VIN = 0 VOL VOH IOL 2.4 -10 0.5 V V IOL = 24 mA IOH = -12 mA VIN = 0 to VCC (Note 1) +10 A VOL VOH IOL 2.4 -10 0.5 V V IOL = 24 mA IOH = -12 mA VIN = 0 to VCC (Note 1) +10 A VOL IOH -10 0.5 +10 V A IOL =48 mA VOH = 0 to VCC (Note 2) VOL VOH IOL 2.4 -10 0.4 V V IOL =24mA IOH = -12 mA VIN = 0 to VCC (Note 1) +10 A VOL VOH IOL 2.4 -1.0 0.4 V V IOL =4mA IOH = -2 mA VIN = 0 to VCC (Note 1) +10 A 138 PARAMETER OD24 Type Buffer Low Output Level Output Leakage OD24P Type Buffer Low Output Level High Output Level Output Leakage OP24 Type Buffer Low Output Level SYMBOL MIN TYP MAX UNITS COMMENTS VOL IOL -10 0.5 +10 V A IOL = 24 mA VIN = 0 to VCC (Note 1) VOL VOH IOL VOL VOH 2.4 -10 25 2.4 -10 0.5 V V IOL = 24mA IOH =-30A VIN = 0 to VCC (Note 1) IOL = 24 mA IOH =-4mA VIN = 0 to VCC (Note 1) All outputs open. Note 3, 4 Chip in circuit: VCC = 0V VIN = 6V Max. +10 0.5 A V V High Output level IOL Output Leakage Supply Current Active Supply Current Standby ChiProtect (SLCT, PE, BUSY, nACK, nERROR) ICC ICSBY IIL +10 35 100 10 A mA A A Note 1: All output leakages are measured with the current pins in high impedance as defined by the PWRGD pin. Note 2: Output leakage is measured with the low driving output off, either for a high level output or a high impedance state defined by PWRGD. Note 3: Defined by the device configuration with the PWRGD input low and 14 MHz clock inactive. Note 4: Max standby supply current given is for Rev. H and K parts. Contact SMSC for Rev. J and all other Revs. CAPACITANCE TA = 25C; fc = 1MHz; VCC = 5V LIMITS PARAMETER Clock Input Capacitance Input Capacitance Output Capacitance SYMBOL CIN CIN COUT MIN TYP MAX 20 10 20 UNIT pF pF pF TEST CONDITION All pins except pin under test tied to AC ground 139 TIMING DIAGRAMS t3 A X, AEN, nIOCS16 nIOR t1 t6 t2 t4 DATA (D0-D7) P D0-PD7, nERR, P E, SLCT, nACK, BUSY FINTR t5 DATA VALID t7 t8 nIOR/nIOW t9 PINTR NOTE: P INTR is the interrupt assigned to the Parallel Port FINTR is the interrupt assigned to the Floppy Disk Pa ram eter t1 t2 t3 t4 t5 t6 t7 t8 t9 A0-A9, AEN, nIOCS16 Set Up to nIOR Low nIOR Width A0-A9, AEN, nIOCS16 Hol d from nIOR H igh Da ta Access Time from nIOR Low D ata to Floa t De lay fro m nIOR High Parall el Port Setup Re ad Stro be to Clear FINTR n IOR or nIOW In active for Transfers to an d fro m ECP FIFO n IOR Active to PINTR Inacti ve m in 40 150 10 typ max units ns ns ns 10 20 40 150 100 60 55 ns ns ns ns ns ns 260 FIGURE 3 - MICROPROCESSOR READ TIMING 140 t3 AX , A EN, nI OC S16 t2 t1 nIOW t4 t5 DAT A (D0-D7) FINTR DATA VALID t6 t7 PI NTR NOTE: PINTR is the interrupt assigned to the Paral lel Port FINTR is the interrupt assigned to the Floppy Disk Parameter t1 t2 t3 t4 t5 t6 t7 A0-A9, AEN , nIOCS16 Set Up to n IOW Lo w nIOW Width A0-A9, AEN , nIOCS16 Ho ld from nIOW High Data Set U p Time to nIOW Hig h Data Ho ld Time from n IOW High Write Strobe to Cle ar FINTR nIOW Inactive to PINTR Inactive min 40 15 0 10 40 10 typ max u nits ns ns ns ns ns ns ns 40 55 26 0 FIGURE 4 - MICROPROCESSOR WRITE TIMING 141 t15 AEN t16 t3 t2 FD RQ, P DRQ FDA CKX PDA CKX t14 t11 nIOR or nIOW t6 t5 t8 t1 t4 t12 t7 DATA (DO-D7) t13 TC DATA VA LID t10 t9 NOTE: FDRQ refers to the DRQ assigned to the Floppy Disk PDRQ refers to the DRQ assigned to the Parall el Port FDACKX r ef ers to t he DRQ as si gned to the to the Floppy Disk PDACKX refers to the DRQ assigned to the Parallel Por t Parameter t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 n DACK Delay Time from FDRQ High DR Q Rese t Del ay fro m nIOR or nIOW FDRQ Reset Delay from nDACK Low nDACK Wid th nIOR Delay from FDRQ High n IOW De lay from FDRQ High Da ta Access Time from n IOR Low Data Set Up Time to nIOW High D ata to Float Delay from nIOR High Data Hold Time from nIOW High n DACK Set Up to nIOW/n IOR Low n DACK Hold Afte r nIOW/nIOR High TC Pulse Width AEN Set Up to nIOR/nIOW AEN Ho ld from n DACK TC Active to PDRQ Inactive min 0 typ max 100 100 units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 150 0 0 40 10 10 5 10 60 40 10 100 60 100 FIGURE 5 - DMA TIMING 142 t1 t2 X1K t4 nRE SET t2 Name t1 t2 t1 t2 t6 Des cription Clo ck Cycl eTime for 14.318MHZ Clock Hig h Time/Low Time for 1 4.318MHZ Clo ck Cycl e Time for 32KHZ Clo ck High Time/Low Time for 3 2KHz Clock Rise Time/Fall Time (not shown) nRESET Low Time min 25 nsec typ m ax 65 Units ns ns ns ns ns ns 5 1.5us NOTE 1: The nRESET low time is depend ent upon the processor clo ck. The n RESET must be active for a min imum of 2 4 x16MHz clock cycle s. FIGURE 6 - CLOCK TIMING 143 t3 nDI R t4 t1 nSTEP t5 nDS0-3 t6 nI NDEX t7 nRDATA t8 nWDAT A nIOW t9 nDS0-1, nM TR0-1 t9 t2 (AT Mode timin g only) Parameter t1 t2 t3 t4 t5 t6 t7 t8 t9 nDIR Set Up to nSTEP Low nSTEP Active Time Low nDIR Hol d Time After nSTEP nSTEP Cycle Time nDS0-1 Hold Time from nSTEP Low nINDEX Pulse Width nRDATA Active Time Low nWDATA Write Data Wi dth Low nDS0-1 , MTR0-1 from En d of n IOW m in typ 4 24 96 132 20 2 40 .5 25 max units X* X* X* X* X* X* ns Y* ns *X speci fi es one MCL K period and Y specifies on e WCLK pe riod . MCLK = Con trol ler Cl ock to FDC (See Table 6 ). WCLK = 2 x D ata Rate (See Table 6 ). FIGURE 7 - DISK DRIVE TIMING 144 nIOW t1 nRTSx, nDTRx t5 IRQx nCTSx, nD SRx, nDCDx t6 t2 IRQx nIOW t4 t3 IRQx nIOR nR Ix Parameter t1 t2 t3 t4 t5 t6 nRTSx, nDTRx Delay from nIOW IRQx Active Del ay from nC TSx, n DSRx, nDC Dx IR Qx Inactive De lay from nIOR (Lea din g Edg e) IRQx Inactive D elay from nIOW (Trailin g Edg e) IRQx Inacti ve D elay from nIOW IRQx Acti ve D elay from nRIx min typ max 20 0 10 0 12 0 12 5 units ns ns ns ns ns ns 10 10 0 10 0 FIGURE 8 - SERIAL PORT TIMING 145 AEN, nIOCS 16 AX t2 t1 nIDEEN, nHDCS x t3 Par ameter t1 t2 t3 n IDEENL O, nIDEEN HI, nH DCSx Delay from AEN, nIOC S1 6 nIDEENLO, nIDEENH I, nHDCSx Delay from AX n IDEEN LO De lay from nIDEENH I, n IOCS16 , AEN min ty p max 40 units ns ns 40 ns FIGURE 9 - IDE INTERFACE TIMING 146 DATA 0 t2 t1 1 0 1 0 0 1 1 0 1 1 t2 t1 IRRX n IRRX Parameter t1 t1 t1 t1 t1 t1 t1 t2 t2 t2 t2 t2 t2 t2 Pul se Wid th a t 115 kbau d Pulse Width at 57 .6 kbau d Pulse Width at 38 .4 kbau d Pulse Width at 19 .2 kbau d Pulse Width at 9.6 kbau d Pulse Width at 4.8 kbau d Pulse Width at 2.4 kbau d Bit Time at 115kbaud Bit Time at 5 7.6kbaud Bit Time at 3 8.4kbaud Bit Time at 1 9.2kbaud Bi t Time at 9.6kbau d Bi t Time at 4.8kbau d Bi t Time at 2.4kbau d min 1.4 1.4 1.4 1.4 1.4 1.4 1.4 typ 1.6 3 .2 2 4.8 9.7 1 9.5 39 78 8 .6 8 1 7.4 26 52 10 4 20 8 41 6 max 2 .7 1 3 .6 9 5 .5 3 11 .0 7 22 .1 3 44 .2 7 88 .5 5 units s s s s s s s s s s s s s s Notes: 1. Re ceive Pulse D etection Cri te ria: A recei ve d pulse i s co nsidered detected i f the recei ve d pulse i s a minimum of 1 .4 1s. 2. IRTX: CRC Bit 0: 1 = RCV active lo w nIRTX: CRC Bit 0: 0 = RCV active hi gh FIGURE 10 - IrDA RECEIVE TIMING 147 DATA 0 t2 t1 1 0 1 0 0 1 1 0 1 1 t2 t1 IRTX nIRTX Parameter t1 t1 t1 t1 t1 t1 t1 t2 t2 t2 t2 t2 t2 t2 Pu lse Width at 1 15kba ud Pulse Width at 57.6kba ud Pulse Width at 38.4kba ud Pulse Width at 19.2kba ud Pulse Width a t 9.6kba ud Pulse Width a t 4.8kba ud Pulse Width a t 2.4kba ud Bi t Time at 115kba ud Bit Time at 57.6kbaud Bit Time at 38.4kbaud Bit Time at 19.2kbaud Bit Time a t 9.6kba ud Bit Time a t 4.8kba ud Bit Time a t 2.4kba ud mi n 1.41 1.41 1.41 1.41 1.41 1.41 1.41 typ 1.6 3.22 4.8 9.7 19.5 39 78 8.68 17.4 26 52 1 04 2 08 4 16 max 2.71 3.69 5.53 1 1.07 2 2.13 4 4.27 8 8.55 units s s s s s s s s s s s s s s No te s: 1. IrDA @ 11 5k is HPSIR compatible. IrDA @ 2400 w ill al low comp ati bil ity with HP95LX and 48 SX. 2. IRTX: C RC Bit 1 : 1 = XMIT active low nIRTX: C RC Bit 1: 0 = XMIT acti ve h igh FIGURE 11 - IrDA TRANSMIT TIMING 148 DATA 0 t1 1 t2 0 1 0 0 1 1 0 1 1 IRTX nIRTX t3 MIRTX t5 nMIRTX t4 t6 Parameter t1 t2 t3 t4 t5 t6 Mod ulated Output Bit Time Off Bit Time Modul ated Output " On" Modul ated Outp ut "Off" Modul ated Output " On" Modul ated Outp ut "Off" min typ max units s s s s s s 0 .8 0 .8 0 .8 0 .8 1 1 1 1 1 .2 1 .2 1 .2 1 .2 N otes: 1. IRTX: CRC Bit 1: 1 = XMIT active low nIRTX: CRC Bit 1: 0 = XMIT active hig h MIRTX, nMIR TX are the modu lated ou tp uts FIGURE 12 - AMPLITUDE SHIFT KEYED IR TRANSMIT TIMING 149 DATA 0 t1 1 t2 0 1 0 0 1 1 0 1 1 IR RX n IR RX t3 MIR RX t5 nMIR RX t6 t4 Parameter t1 t2 t3 t4 t5 t6 Mo dula ted Ou tpu t Bit Time Off Bit Time Modu lated Output "On" Modu lated Output "Off" Modu lated Output "On" Modu lated Output "Off" min typ max units s s s s s s 0.8 0.8 0.8 0.8 1 1 1 1 1.2 1.2 1.2 1.2 Notes: 1. IRRX: CRC Bit 0: 1 = RC V active low nIRR X: CRC Bit 0: 0 = RCV active hi gh MIRRX, nMIRRX are the modulated o utputs FIGURE 13 - AMPLITUDE SHIFT KEYED IR RECEIVE TIMING 150 PD0- P D7 t6 nI O W t1 nINIT, nSTROBE. nAUTOFD, SLCTIN PIN TR (SP P) nACK t2 PI NTR (ECP or EPP E nabled) nF AULT (ECP) nERROR (E CP) t5 t2 PI NTR t3 t4 t3 Par ameter t1 t2 t3 t4 t5 t6 nINIT, n STROBE, nAUTOFD Dela y from nIOW Inactive PINTR Del ay from nACK, nFAUL T PIN TR Active Low in ECP an d EPP Mo des PINTR Delay from nACK n ERROR Active to PIN TR Active PD0-PD7 D elay from nIOW Active NOTE: min typ m ax 1 00 60 3 00 1 05 1 05 1 00 units ns ns ns ns ns ns 2 00 PI NTR is the i nt errupt assigned to the Parallel Port FIGURE 14 - PARALLEL PORT TIMING 151 t 18 AX t9 SD<7:0> t 17 t8 nIOW t 10 IO CH RDY t 13 t 20 nWR ITE t1 PD<7: 0> t 14 nDATAST nADDRSTB t6 nWAIT t 15 t7 t 16 t3 t4 t5 t2 t 11 t 12 t 19 Parameter t1 t2 t3 t4 t5 t6 t7 t8 t9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 1. nIOW Ass erted t o PDA A Valid T nWAIT As sert ed to nWRITE Change nWR ITE to Command As sert ed nWAI T Deass erted to Command Deasserted nWAI T Asserted t o PD ATA Inv alid Time O ut Command D easserted to nWAIT Asserted SDA Valid to IOW As sert ed TA nIOW Deasserted to DATA Inv alid nIOW Ass erted t o IOC HRDY As sert ed WAI T Deass er ted to nI OCH RDY Deas sert ed I OCH RDY Deassert ed to nIOW Deas sert ed nIOW Asserted to nW RITE As sert ed nWAIT As sert ed to Command As sert ed Command Asserted to nWAIT Deas sert ed PDATA Valid to Command As sert ed Ax Valid t o nIO W As sert ed nIOW Deas ser ted to Ax Inv alid nIOW Deasserted to nIOW or nIOR Asserted nWA IT Ass er ted t o nWR ITE Ass erted min 0 60 5 60 0 10 0 10 0 0 60 10 0 60 0 10 40 10 40 60 max 50 185 35 190 12 units ns ns ns ns ns s ns ns ns ns ns ns ns ns s ns ns ns ns ns Not es 1 1 1 24 160 70 210 10 1 1 185 1 WAIT must be filt er ed to compens at e f or ringing on the paralle l bus cable. WAIT is considered to have settled aft er it does not t ransition for a minimum of 50 ns ec. FIGURE 15 - EPP 1.9 DATA OR ADDRESS WRITE CYCLE 152 t20 AX t19 IOR t13 SD<7:0> t8 IOCHRDY t9 t21 nWRITE t2 t25 PD<7:0> t28 t1 t14 DATASTB ADDRSTB t15 t7 nWAIT t6 t3 t5 PData bus driven by peripheral t11 t12 t18 t10 t22 t17 t4 t16 Timin g paramete r tabl e fo r the EPP Data or Addre ss Read Cycl e is found on next pag e. FIGURE 16A - EPP 1.9 DATA OR ADDRESS READ CYCLE 153 Parameter t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t25 t28 PDATA Hi-Z to Comman d Asserted nIOR Asserted to PD ATA Hi -Z nWAIT Deasser ted to Comma nd Dea sserted Comma nd Dea sserted to PDATA Hi-Z C ommand Asser ted to PDATA Val id PDAT Hi-Z to n WAIT Deasserted A PDATA Val id to n WAIT Deasserted n IOR Assertd to IOCHRDY Asserted nWR ITE Deasser te d to n IOR Asserted nWAIT Deasserted to IOCHRD Y Dea sserted IOCHRDY Dea sse rted to n IOR Dea sserted nIOR De asserted to SDATA Hi-Z (Ho ld Time) PD ATA Valid to SDATA Val id nWAIT Asserted to Comman d Asserted Time Ou t nWAIT De asserted to PDATA D riven nWAIT Deasser ted to nWRITE Modi fied SDATA Val id to IOCHR D Dea sserted Y Ax Vali d to nIOR Asserted nIOR Deasserted to Ax Invalid nWAIT Asserted to nWRITE Deasserted nIOR D easser te d to nIOW or nIOR Asserted n WAIT Asserted to PDATA Hi-Z WRITE Deasserted to Co mma nd min 0 0 60 0 0 0 0 0 0 60 0 0 0 0 10 60 60 0 40 10 0 40 60 1 max 30 50 1 80 units ns ns ns ns ns s ns ns ns ns ns Notes 1 24 1 60 2 1 40 75 1 95 12 1 90 1 90 85 10 1 85 1 80 ns ns ns s ns ns ns ns ns ns ns ns ns 1 1,2 3 1 1 . n WAIT is consi dere d to ha ve settled a fter it does no t transition for a min imum of 50 ns. 2. When not executing a write cycle, EPP nWRITE is in acti ve h igh . 3. 8 5 is tru e o nly if t7 = 0 . FIGURE 16B - EPP 1.9 DATA OR ADDRESS READ CYCLE TIMING PARAMETERS 154 AX t18 t9 SD<7:0> t17 t8 t6 t12 t19 nIOW IOCHRD Y t10 t20 t11 nWRITE t13 t2 t1 PD<7:0> t16 t3 t5 nDATAST nAD DRSTB t4 nWAIT t21 Param eter t1 t2 t3 t4 t5 t6 t8 t9 t 10 t 11 t 12 t 13 t 16 t 17 t 18 t 19 t 20 t 21 nIOW Ass erted t o PDA A V T alid Command D esssert ed to nWRI TE Change n WRITE to Command nI OW De ass erted to Co m mand De assert ed Command Deasserted to PDATA Invalid Time Out SDATA Valid t o nIOW As sert ed nIOW Deasserted to DATA Inv alid n IOW Ass erted t o IOCHRDY As se rt ed n WAIT Deassert ed to IOCHRDY Deas sert ed I OCH RDY Deassert ed to nIOW De assert ed nIOW As serted to nW RITE Asserted PDA Valid to Comm TA and As se rt ed Ax Valid to nIOW As sert ed nIOW De as serted to Ax Inv alid nIOW Deasserted to nIOW or nIOR Asserted n WAIT As serted to IOCHRD Deasserted Y Command Deasserted to nWAIT Deas sert ed min 0 0 5 50 10 10 0 0 10 0 10 40 10 100 0 max 50 40 35 50 12 units ns ns ns ns ns s ns ns ns ns ns ns ns ns s ns ns ns N ot es 2 24 40 50 35 45 1 . WRITE is controlled by clearing the PDIR b it to "0" in the contro l register be fore performin g an EPP Write. 2. This number is only valid i f WAIT is active whe n nIOW g oes active. FIGURE 17 - EPP 1.7 DATA OR ADDRESS WRITE CYCLE 155 t20 AX t15 nIOR t19 t11 t22 t13 S D<7:0> t12 t8 IOCHRDY t3 t10 nWRITE t5 P D<7:0> t4 nDATAS TB t23 t2 nADD RS TB t21 nWAIT Parameter t2 t3 t4 t5 t8 t10 t11 t12 t13 t15 t19 t20 t21 t22 t23 nIOR Deas sert ed to Command Deass erted nWAIT Asserted to IOC HRDY D eass erted Com mand Deasserted to PDATA Hi-Z Command Asserted to PDATA Valid nIO R As serted to IOCHRDY Asserted nWA IT Deasserted to nIOCHRDY Deasserted nIOC HRDY D easserted to nIO R D eass erted nI OR Deas serted to SDATA Hi gh-Z (Hold Time) PData V alid to SDATA Valid Time Out Ax V alid to nI OR Asserted nIO R Deassert ed to Ax Invalid Command Deasserted to nWAIT Deasserted nIOR Deass erted to nI OW or nI OR Asserted nI OR Asserted t o C ommand Asserted min max 50 40 unit s ns ns ns ns ns ns ns ns ns s ns ns ns ns ns Notes 0 0 0 24 50 0 0 10 40 10 0 40 40 40 12 55 1 . nWRITE is controll ed by setti ng the PDIR bit to "1 " i n th e control register before performing an EPP R ead . FIGURE 18 - EPP 1.7 DATA OR ADDRESS READ CYCLE 156 ECP PARALLEL PORT TIMING Parallel Port FIFO (Mode 101) The standard parallel port is run at or near the peak 500 Kbps allowed in the forward direction using DMA. The state machine does not examine nAck and begins the next transfer based on Busy. Refer to Figure 19. ECP Parallel Port Timing The timing is designed to allow operation at approximately 2.0Mbytes/sec over a 15ft cable. If a shorter cable is used then the bandwidth will increase. Forward-Idle When the host has no data to send it keeps HostClk (nStrobe) high and the peripheral will leave PeriphClk (Busy) low. Forward Data Transfer Phase The interface transfers data and commands from the host to the peripheral using an interlocked PeriphAck and HostClk. The peripheral may indicate its desire to send data to the host by asserting nPeriph Request. The Forward Data Transfer Phase may be entered from the Forward-Idle Phase. While in the Forward Phase the peripheral may asynchronously assert the nPeriph Request (nFault) to request that the channel be reversed. When the peripheral is not busy it sets PeriphAck (Busy) low. The host then sets HostClk (nStrobe) low when it is prepared to send data. The data must be stable for the specified setup time prior to the falling edge of HostClk. The peripheral then sets PeriphAck (Busy) high to acknowledge the handshake. The host then sets HostClk (nStrobe) high. The 157 The interface transfers data and commands from the peripheral to the host using an interlocked HostAck and PeriphClk. The Reverse Data Transfer Phase may be entered from the Reverse-Idle Phase. After the previous byte has beed accepted the host sets HostAck (nAutoFd) low. The peripheral then sets PeriphClk (nAck) low when it has data to send. The data must be stable for the specified setup time prior to the falling edge of PeriphClk. When the host is ready it to accept a byte it sets. HostAck (nAutoFd) high to acknowledge the handshake. The peripheral then sets PeriphClk (nAck) high. After the host has accepted the data it sets HostAck (nAutoFd) low, completing the transfer. This sequence is shown in Figure 21. OutputDrivers To facilitate higher performance data transfer, the use of balanced CMOS active drivers for critical signals (Data, HostAck, HostClk, PeriphAck, PeriphClk) are used ECP Mode. Because the use of active drivers can present peripheral then accepts the data and sets PeriphAck (Busy) low, completing the transfer. This sequence is shown in Figure 20. The timing is designed to provide 3 cable round-trip times for data setup if Data is driven simultaneously with HostClk (nStrobe). Reverse-Idle Phase The peripheral has no data to send and keeps PeriphClk high. The host is idle and keeps HostAck low. Reverse Data Transfer Phase compatibility problems in Compatible Mode (the control signals, by tradition, are specified as open-collector), the drivers are dynamically changed from open-collector to totem-pole. The timing for the dynamic driver change is specified in the IEEE 1284 Extended Capabilities Port Protocol and ISA Interface Standard, Rev. 1.09, Jan. 7, 1993, available from Microsoft. The dynamic driver change must be implemented properly to prevent glitching the outputs. t6 t3 PDATA t1 nS T ROBE t4 BUSY t2 t5 Parameter t1 t2 t3 t4 t5 t6 DATA Vali d to nSTROBE Active nSTROBE Active Pulse Width DATA Hold from nSTROBE Inactive n STROBE Active to BUSY Active BUSY In active to nSTROBE Active BUSY In active to PDATE Invalid min 6 00 6 00 4 50 max units ns ns ns ns ns ns Notes 1 5 00 6 80 80 1 1. The da ta i s h eld un ti l BUSY go es inactive or for ti me t3, whi ch ever is long er. Th is o nly ap plie s i f ano th er data tra nsfer is pending. If no other data transfer is p end ing, th e data is h eld i ndefin itely. FIGURE 19 - PARALLEL PORT FIFO TIMING 158 t3 nAUTOFD t4 PDA TA<7:0> t2 t1 t7 nS TROBE t6 BUSY t5 t6 t8 Parameter t1 t2 t3 t4 t5 t6 t7 t8 n AUTOFD Va lid to nSTROBE Asserted PDATA Va lid to nSTROBE Asserted BUSY Deasserted to nAUTOFD Cha nged n BU SY Deasser ted to PDATA Cha nged nSTROBE Asserted to BUSY Asserted nSTR OBE Dea sse rted to Bu sy De asserted nBUSY Deasser te d to n STROBE Asserted nBUSY Asserted to nSTR OBE De asserted min 0 0 80 80 0 0 80 80 max 60 60 180 180 units ns ns ns ns ns ns ns ns Notes 1 ,2 1 ,2 200 180 1 ,2 2 1 . Maximum valu e only ap plie s if there is da ta i n th e FIFO waitin g to b e writte n out. 2. BUSY is no t consi dered asserted or de asserted u ntil it is stable for a min imum of 7 5 to 1 30 ns. FIGURE 20 - ECP PARALLEL PORT FORWARD TIMING 159 t2 PDATA<7: 0> t1 t5 nACK t4 nAUTOFD t3 t4 t6 Parameter t1 t2 t3 t4 t5 t6 PDATA Va lid to nACK Asserted nAUTOFD Deasserte d to PDATA C hang ed nACK Asse rte d to n AUTOFD Deasserted nACK D easser te d to n AUTOFD Asserted n AUTOFD Asserted to nACK Asserted nAUTOFD De asser ted to nACK Deasserted min 0 0 80 80 0 0 max units ns ns Notes 2 00 2 00 ns ns ns ns 1,2 2 1. Maximum va lue on ly appl ies if th ere is room in the FIFO a nd a terminal count has no t b een rece ived. ECP can stal l b y kee pin g nAU TOFD lo w. 2. nACK is not consid ered asserted or dea sserted un ti l i t is stable for a minimum of 75 to 130 ns. FIGURE 21 - ECP PARALLEL PORT REVERSE TIMING 160 D D1 E E1 e W A H 0. 10 -CD IM A A1 A2 D D1 E E1 H L L1 e 0 W TD(1) TE(1) TD(2) TE(2) A2 TD /TE 0 A1 MIN MAX 2. 80 3. 15 0.1 0. 45 2. 57 2. 87 23 .4 24. 15 19 .9 20 .1 17 .4 18. 15 13 .9 14 .1 0.1 0.2 0. 65 0. 95 1.8 2.6 0.65 BSC 0 12 .2 .4 21 .8 22 .2 15 .8 16 .2 22. 21 22. 76 16. 27 16. 82 MAX MIN .1 24 .1 10 .0 18 .0 04 .1 13 .1 01 .9 51 .9 21 .7 91 .7 83 .7 15 .6 85 .5 55 .5 47 .0 08 .0 04 .0 37 .0 26 .1 02 .0 71 .0256 BS C 0 12 .0 08 .0 16 .8 58 .8 74 .6 22 .6 38 .8 74 .8 96 .6 41 .6 62 L L1 Not es : 1) C oplanarity is 0.1 0 0mm (. 00 4") maximum. 2) Toleranc e on th e posit ion o f the leads is 0.2 00mm (. 00 8") maximum. 3) Pack age body d imensions D1 and E1 do not include the mold pro trus ion. Ma ximum mold pr otrusio n is 0 .25mm (. 01 0"). 4 ) Dimensions TD and TE are impo rt ant f or testing by robotic ha n dler. Only above c ombinatio ns of (1) or (2) are acc eptable. 5) Cont rolling dimension: millimeter . D imensions in inches for reference only and not n ec es sarily accurate. FIGURE 22 - 100 PIN QFP PACKAGE OUTLINE 161 D 3 D1 3 e E E1 5 D1/4 E1/4 DETAIL "A" R1 R2 A H SEE DETAIL "A" 1 -C0.10 A1 DIM A A1 A2 D D1 E E1 H L L1 e 0 W R1 R2 MIN 0.05 1.35 15.75 13.90 15.75 13.90 0.45 NOM MAX 1.6 1.45 16.25 14.10 16.25 14.10 0.20 0.75 A2 4 L L1 0 W 2 1.40 16.00 14.00 16.00 14.00 0.60 1.00 0.50 BSC 0.25 0.20 0.20 0 8 Notes: 1 Coplanarity is 0.100mm maximum. 2 Tolerance on the position of the leads is 0.13mm maximum. 3 Package body dimensions D1 and E1 do not include the mold protrusion. Maximum mold protrusion is 0.25mm per side. 4 Dimension for foot length L are measured at the gauge plane 0.25mm above the seating plane. 5 Details of pin 1 identifier are optional but must be located within the zone indicated. 6. Controlling dimension: millimeter FIGURE 23 - 100 PIN TQFP PACKAGE OUTLINE 162 FDC37C669 ERRATA SHEET PAGE 1 4 5 - 14 14 15 119 136 136 136 - 139 1 139 SECTION/FIGURE/ENTRY Features CORRECTION All references to 3.3V operation have been removed DATE REVISED 3/14/96 3/14/96 3/14/96 3/14/96 3/14/96 3/14/96 3/14/96 3/14/96 3/14/96 8/4/99 8/4/99 PIN CONFIGURATION/Pin No. "VI/O" changed to "NC" 98 Description of Pin Functions Buffer Type Descriptions Block Diagram Table 46/Last Row MAXIMUN GUARANTEED RATINGS DC ELECTRICAL CHARACTERISTICS Entire Table Features DC Electrical Characteristics See Italicized Text See Italicized Text All references to 3.3V operation have been removed "IRQ Share" taken out See Italicized Text "3.3V" changed to "5V" See Italicized Text See Italicized Text See Italicized Text 163 80 Arkay Drive Hauppauge, NY 11788 (631) 435-6000 FAX (631) 273-3123 Copyright (c) SMSC 2004. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC's website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems Corporation ("SMSC"). Product names and company names are the trademarks of their respective holders. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. FDC37C669 Rev. 03-22-00 |
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